ASIC Stoic: Cadence Virtuoso CMOS Analog Design Basics in TSMC 22nm: a simple op-amp design with a High Swing Cascode current mirror

Cadence Virtuoso CMOS Analog Design Basics in TSMC 22nm: a simple op-amp design with a High Swing Cascode current mirror

In the previous blog post “Cadence Virtuoso CMOS Analog Design Basics in TSMC 22nm: “Constant gm bias circuit” with start-up and reduced sensitivity
to changes in VDD” we needed to add an opamp.

A design of a simple opamp is very well explained by Hafeez KT, in his youtube lecture available online and here is a basic topology:

But even the simplest opamp schematic would need a current mirror ( NMOS transistors M5 and M8 ) provide necessary referent current Io .

In this blog post I would like to explore a High Swing Cascode current mirror a subject very well explained by prof. Nagendra Krishnapura in his lectures
available online ( ee5320 2016 IIT Madras ).

For a “short channel” processes ( or other name is a nanometer process ) such as TSMC 22nm , we should always use High Swing Cascode because
ID5 is very dependant on VDS5 .

E.g. For VDS1=VDD = 3.3 , a change between VGS1=VGS2=1.094V to 3.6V is causing change of ID1 between: 10uA to 10.55uA. Expected value
ID2=ID1 = 10uA is true only if VDS1=VDS2=VGS1=VGS2=1.094V.

Variation of ID1 with a variation of VDD=VDS1 is no surprise because it can be proven that output resistance of M1 ( the resistance “seen” to the drain of M2 transistor) is 1/gds2 .

=> for a change of a delta Vout=VDS1 =>IDS1 changes to IDS1 + delta VDS1*gds2

Since for NMOS transistor M2 in saturation gm is:

=> there are two solutions to the problem of the small output resistance:

somehow increase the output resistance or
decrease gm ( or decrease W, or increase L or increase ID2=ID1=Io=10uA )

Decreasing gm is not really an option because our referent current is 10uA and we don’t want to “burn” more current/power. On the other hand W/L of transistors M1 and M2 is
W/L=1u/2u, a reasonable small W and a reasonable big value of L.

=> The solution is an increase of output resistance.

One of the solutions is to use a current buffer ( NMOS transistor M3 ). Current buffer would be a device that gives you the same current but a much higher output resistance.

A common gate stage is a current buffer ( cascoded transistor )

Biasing of NMOS transistor M3 could be found by “sweep” of V1= VG3 and at the same time observing ID1 to reach ID2=ID1=10uA.

The “sweep” value of V1=VG3 to reach ID2=ID1=10uA is V1=VG3=2.441V which is in line with a following hand calculation:

Ideally M2 drain voltage should be VGS1 ( so M1 and M2 could be exactly the same and Id1 = Id2 = I0 ) and in reality M2 drain voltage is
VG3 - VGS3 => ideally VGS1 = VG3 - VGS3
=> VG3 = VGS1 + VGS3

From simulation: VG3 = VGS1(1.094V) + VGS3(1.337V) = 2.441V

Finally we achieved a much better stability of IDS1 in relation to variation of VDD:

For a V0=Vout change from 1.18V to 3.6V, IDS1 change is from 9.99uA to 10uA:

Using cascoded transistor M3, we increased output resistance hence better result of the stable ID2=ID3=10uA with a variation of V0=Vout

Note*: The simulation shows that for this topology schematic developed so far, V0=Vout minimum is around 1.18V which is high when we consider that alim. voltage
VDD=3.3V

As a quick hand calculation of the new increased output resistance, it can be proven that the output resistance of a common source with degeneration is:

As a conclusion, since gm3*rds3*Rs >> Rs+rds3 a reasonable assumption is that output resistance in cascoded case is gm3*rds3*rds2:

=> for a change of a delta Vout =>IDS1 changes to IDS1 + delta VDS1/(gm3*rds3*rds2)

This is much less of IDS1 change comparing to the “non-cascode” original case

To get biasing VG3 = VGS1 + VGS3 we will add one more cascoded NMOS transistor M4 ( diode connected) at the branch of M1, and the size of M4 should be the
same as the size of M3:

And now let’s get even more ambitious: here is now a calculation of a minimum voltage Vout so both ( simple and cascode ) current mirror to be operational

cascode minimum voltage is much higher than one in simple current mirror

For a simple ( non cascoded ) current mirror Vout must be always greater than VDsat of M2 ( based on ID1=10uA ):

And for the cascoded case:

A minimum Vout for the current mirror to be operational:

Vout - VS4 > VG4 -VS4 -Vth

=> Vout > VG4 -Vth

VG4 = VGS1 +VGS3

=> Vout > VGS1 +VGS3 -Vth

=> Vout > ( VGS1 -Vth) +( VGS3 -Vth ) +Vth

=> Vout > VDS1(saturation ) + VDS3(saturation ) + Vth

As a conclusion, by populating the Vout minimum expression with the simulation results and under assumption that Vth is approx. 760mV we are expecting for
the current topology/schematic Vout minimum is :

Vout > 388mV + 406mV + 760mV = 1.556V

Since our alim. VDD=3.3V and so far for the current topology/schematic Vout min is approx. 1.556V the conclusion is: we don't have that much of a “headroom”.

=> So, what we would really like is a solution with a minimum possible value for the Vout min.

What is the minimum Vout for the current mirror to be operational ?

A friendly reminder: A minimum Vout for the current mirror to be operational is driven by a minimal VG3 since:

Vout > VG3 - Vth

What should it be a bias voltage of M4 (VG3 = ?), but it’s minimum value to remove any inefficiency ?

To achieve minimum VG3, a necessary condition is that M2 and M3 are in saturation ( VDS2 = VDS2(saturation) and VDS3 = VDS3(saturation) )

=> VG3 = VGS3 ( when I0 current is flowing through M3,M2 ) + VDS2(saturation, again when I0 current is flowing through M3,M2 )

VG3 = VGS3 +VDS2 sat

Also in the case of the minimum VG3, the minimum voltage Vout = VDS2( saturation, with I0 flowing through M2,M3) + VDS3( saturation, with Io=10uA flowing through M2,M3).

=> according to our simulations so far we could expect for minimum VG3:

Vout > 388mV + 406mV meaning: Vout min = approx. 800mv

Our bias task related to M3, is to find what is ( and how to implement it ) VG3 = VGS3 ( when Io=10uA current is flowing through M2,M3 ) + VDS2(saturation, again when Io
current is flowing through M2,M3 ).

=> VG3 = VGS3 + VDS2(saturation)

VDS3(saturation) > VGS3 -Vth

since VGS3 -Vth = VG3 -VS3 -Vth and VS3 = VDS2(saturation)

=> VGS3 -Vth = VG3 - VDS2(saturation) -Vth

=> VDS3(saturation) > VG3 - VDS2(saturation) -Vth

=> VG3 > VDS3(saturation) + VDS2(saturation) + Vth

=> VG3 minimum = VDS3(saturation) + Vth + VDS2(saturation)

Since:

Under assumption that sizes M3=M2 meaning both has the same W/L and Id3=Id2=10uA

=> VG3 minimum = Vth + 2* VDS

=>VG3 = Vth + 2*2I0/(*Cox*W/L)

=>VG3 = Vth + 2I0/(*Cox*(W/4)/L)

What is 2I0/(*Cox*(W/4)/L) ?

e.g. one way to look at this: 2I0/(*Cox*(W/4)/L) is a VDS( or Vov: “overdrive voltage”) of a transistor in saturation that has Id=I0 current, and has dimensions (W/4)/L .

In general, when faced with a need to generate a voltage Vth + something ( e.g.Vov ) we can use this structure, which is a transistor connected as a diode and always in guaranteed saturation:.

VDS = VGS and VDS saturation > VGS -Vth => always is true that VGS > VGS - Vth => the transistor is always in saturation )

Also “sweeping” Vout=V0 shows that Vout minimum is around 0.8V in line with our hand calculation:

But there is a problem here: VDS1 (M1 transistor) and VDS2 (M2 transistor but minimum VDS2 to keep M2 in saturation ) are not the same and Id3=Id2 of approx 9.57uA
will not be exactly Id1=10uA.

This is because of the influence of channel length modulation, in other words there will always a systematic error. So this schematic is good but it would be better if VDS1 = VDS2.

VDS2 is VDsat and VDS1 is VGS1 ( and VGS1 = VDsat + Vth )

So again the problem is how to implement a circuit to give us a perfect VGS1 to produce exactly VDS1 = VDS2 => Id3=Id2 equal exactly 10uA.

Let’s say we can find a perfect VGS1 ( to produce exactly VDS1 = VDS2 => Id3=Id2 equal exactly 10uA ) using a circuit like this:

An equivalent circuit exists if we have a current source Io and transistor M1 how do we insure that Id1=10uA. We could take a voltage generator VG1 and adjust VGS1
to be exactly the value so Id1=10uA: