Cadence Virtuoso CMOS Analog Design Basics: an schematic for generating a reference current ( e.g. 10uA ) in a new techno ( e.g. TSMC 22nm ) using “Constant gm bias circuit” with start-up

Cadence Virtuoso CMOS Analog Design Basics: an schematic for generating a reference current ( e.g. 10uA ) in a new techno ( e.g. TSMC 22nm ) using “Constant gm bias circuit”  with start-up

In the previous blog post: “Cadence Virtuoso CMOS Analog Design Basics: an example of adding
a schematic for generating a reference current ( e.g. 10uA ) in a new techno ( e.g. TSMC 22nm )”
I used self-biased circuit but without adding start-up circuit.

This is where we left off in the previous blog post and now we are going to add a startup circuit:

In any self-biased  circuit there are two  possible operating points:  wanted one
( in our case the self-biased  circuit will generate 10uA current) and the  unwanted one
where no current flows in the  circuit. 

Note*: Equations presented in the previous blog entry gave us a hint about the existence of
these two possible operating points in this circuit:

And after division of both sides of the equation with Iref under assumption that Iref is not equal to 0:

But equation:

is also true when Iref=0 meaning that the circuit will have two possible states ( stable points ) 
after power up and one of them is an undesirable state where Iref=0.

In our schematic when Iref=0 (an undesired state  of the circuit) NMOS transistors M4 and M5 are not
conducting so it is safe to say that gates voltage of NMOS transistors M4 and M5 are VG4=VG5 is
approx. 0V. 

On the other hand again Iref=0 (an undesired state  of the circuit) because of the effect of
forward biased diode of transistor M6,  it is also safe to say that gate voltage of PMOS transistors
M7 and M6,VG6=VG7 is approx. VDD=2.5V.

• So to be sure that our self-biased circuit never get “stuck” into undesirable state resulting in

Iref=0 we need to add a circuit ( a “start-up” circuit ) that will put/”leak” some current into the

drain of NMOS transistor M5 in the case that VG4=VG5 approx. 0V and  VG6=VG7 approx.

VDD=2.5V a consequence of undesirable but stable state anyway of the self-biased circuit

with Iref=0.

• We also need that “start-up” circuit  to stop “leaking” the current into the drain of NMOS

transistor M5 when mission of “start-up” is accomplished in other words when our

self-biased circuit move from a stable state where Iref=0 to other stable state where

Iref=10uA.

Exact way of thinking that led to schematic of the start-up circuit is very well explained by
prof. Jacob Baker in his class lectures available online, but here I would start with a simple topology
that use an unreasonable big resistor( for example 100M ) and two transistors:

•  NMOS M9 used as switch ( a hint: small L ) and provider of “leakage” current to drain of

NMOS transistor M5 when there is the stable state of self-bias circuit resulting in  Iref=0 and

cutting the current “leakage” when there is the stable state of self-bias circuit

resulting in Iref=10uA.

• NMOS transistor M10 is biasing to ON transistor M9 when there is the stable state of

self-bias circuit resulting in  Iref=0 and M10 is biassing to OFF transistor M9 when there is

the stable state of self-bias circuit resulting in Iref=10uA.

• NMOS transistor M10 shares the same VGS with NMOS transistor M5 in

a current mirror configuration and  M10 and M5 are the same size W/L.

A transient simulation shows that transistor M9 is providing a lot of current at the beginning of
simulation when  ID5=Iref=0 and when the circuit settles in the desired stable state when
ID5=Iref=10uA, transistor M9 is “leaking” into drain of M5 only approx. 0.8uA:

  

Note*: in order to get the transient simulation as presented in the waveform above it is necessary to
setup initial conditions on two nets in Cadence Virtuoso Spectre like this:

ADE->Simulation->Convergence Aids->Initial Condition

The initial condition  of gate voltage of NMOS transistors M4 and M5 is VG4=VG5 =0V and the
second initial condition is on gate voltage of NMOS transistors M6 and M7 and it is
VG6=VG7 approx. VDD=2.5V.

It is not practical to have unreasonable big resistor in a circuit, so in a final schematic resistor
R=100M is replaced with two diode connected transistors M11 and M12 sized with smallest
W=1um and largest L=500um:

  Or another better version of the same circuit:

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