Verilog RTL verification

CoCoTB based verification: A small example is getting bigger

CoCoTB: A Simple DUT and (almost) complete randomized, self-checking Testbench/Test with (some) coverage reporting

Introduction

In a last blog post dedicated to CoCoTB and titled "CoCoTB based verification: A small example(https://asicstoic.blogspot.com/2023/06/cocotb-based-verification-small-example.html#comment-form) there is an introduction to CoCoTB (Coroutine-based Co-simulation Test Bench), an open-source Python library used for hardware design verification and testing. The post provides a small example of a CoCoTB testbench/test implemented using the icarus simulator and explains CoCoTB’s key concepts and features.In the last post there is also an explanation of the directory structure and Makefile to facilitate running the simulation . All of this is not going to be repeated in this blog post.

In this blog post files involved are:

DUT module with handshake controls on both input data and output data side (SimpleDUT_hs.v),
wrapper module (SimpleDUT_hs_test.v) for collecting a VCD file, and
Python/CoCoTB testbench/test (SimpleDUT_hs_test.py).

Here is a source code of the blog post files

SimpleDUT_hs.v (The DUT)

As the DUT in the previous blog post, the new DUT (SimpleDUT_hs.v) module has a single data 4-bit input port (din_i) and a corresponding 4-bit output data port (dout_o). The data functionality of the DUT is straightforward, as dout_o is always equal to din_i.

However, what sets this version of the DUT apart is the addition of handshake control signals, which streamline the flow of data to and from the DUT.

To facilitate the transfer of input data, we have incorporated the en_din_i DUT input port and the rdy_din_o DUT output port. Similarly, for sending out the DUT result data, we employ the rdy_dout_i DUT input port and the en_dout_o DUT output port. These handshake control signals establish a seamless and coordinated data exchange process and the DUT has no internal data storage capability.

Despite the inclusion of these handshake control signals, the basic functionality of the DUT remains as before straightforward. To repeat once again The DUT output port, dout_o, always mirrors the value of the DUT input port, din_i.

The handshake protocol employed in this module is fairly simple. When a producer of data has a data ready for transmission, it assigns "en_*" to 1. On the other hand, when a consumer is prepared to receive the data, it responds by assigning "rdy_*" to 1.

In one pair of handshake control signals: "rdy_*" cannot transition to 1 unless its corresponding "en_*" is already 1. When a producer has data ready for transmission ("en_*" = 1) the data transmission is stalled until corresponding consumer becomes ready to accept the data ( "rdy_*" change from 0 to 1 and stay 1 one clock cycle ). The reason for this , as mentioned before, is that the DUT has no internal data storage capability.

The other assumptions about DUT:

It is fully synchronous design on it’s main ( and only ) system clock: DUT input port: CLK
Power On reset (DUT input port: RST_N) is active low
handshake control signals and in and out data bus values are also synchronous to DUT main system clock.

module SimpleDUT_hs (
input CLK,
input RST_N,

input en_din_i,
output rdy_din_o,
input [3:0] din_i,

input en_dout_i,
output rdy_dout_o,
output [3:0] dout_o
);

// Define the states using localparam
localparam START_ST = 1'b0;
localparam WR_ST = 1'b1;

reg rdy_dout_o , next_rdy_dout ;
reg en_o , next_en ;
reg[3:0] dout_o, next_dout ;
reg rdy_din_o ;

reg state, next_state ;

always @(posedge CLK or posedge RST_N) begin
if (!RST_N) begin
state <= START_ST;
rdy_dout_o <= 1'b0 ;
dout_o <= 4'd0 ;
end else begin
state <= next_state ;
rdy_dout_o <= next_rdy_dout ;
dout_o <= next_dout ;
end
end

always @(*) begin
next_state = state ;
next_rdy_dout = rdy_dout_o;
next_dout = dout_o;

rdy_din_o = 1'b0;
case(state)
////////////////////////////
START_ST: begin
if(en_din_i) begin
next_dout = din_i;
rdy_din_o = 1'b1;

next_rdy_dout = 1'b1;

next_state = WR_ST;
end
end

///////////////////////////
WR_ST: begin
case({en_din_i, en_dout_i})
2'b00, 2'b10:
next_state = state ;
2'b01: begin
next_rdy_dout = 1'b0;
next_state = START_ST;
end
2'b11: begin
next_dout = din_i;
rdy_din_o = 1'b1;
end
endcase

end
endcase
end

endmodule

As in the previous blog post there is a “wrapper” for the DUT (SimpleDUT_hs_test.v) just to add a capability to collect VCD file (SimpleDUT.vcd) to later display waveforms of verification/simulation run:

module SimpleDUT_hs_test (
input CLK,
input RST_N,

input en_din_i ,
output rdy_din_o ,
input [3:0] din_i ,

input en_dout_i ,
output rdy_dout_o ,
output [3:0] dout_o
);

SimpleDUT_hs dut (
.CLK (CLK ),
.RST_N (RST_N ),

.en_din_i (en_din_i ),
.rdy_din_o (rdy_din_o ),
.din_i (din_i ),

.en_dout_i (en_dout_i ),
.rdy_dout_o(rdy_dout_o ),
.dout_o (dout_o )
);

initial begin
$dumpfile("SimpleDUT_hs.vcd");
$dumpvars;
end
endmodule

A Python/CoCoTB testbench for the DUT verification integrated with a self-checking/randomized test ( with some coverage reporting capability): SimpleDUT_hs_test.py

1 import cocotb
2 from cocotb.clock import Clock
3 from cocotb.triggers import Timer, RisingEdge, ReadOnly, NextTimeStep, FallingEdge, Event
4 from cocotb_bus.drivers import BusDriver
5 from cocotb.result import TestFailure
6 import random
7 import warnings
8 from collections import deque
9 from cocotb_coverage.coverage import CoverCross, CoverPoint, coverage_db
10 from cocotb_coverage import coverage
11 import os
12 # Here are two coverage points defined using the cocotb_coverage library. These coverage points are essential for tracking and analyzing the values of DUT handshake control ports en_din_i and rdy_din_o during the simulation. By specifying the signal names and defining bins, we can effectively monitor the signal's behavior and identify any gaps or discrepancies in its values.
13 @CoverPoint("top.en_din_i", bins=[0,1])
14 def en_din_i_cover(en_din_i):
15 pass
16
17 @CoverPoint("top.rdy_din_o", bins=[0,1])
18 def rdy_din_o_cover(rdy_din_o):
19 pass
20 # A coverage cross is defined to capture the cross coverage between DUT handshake control ports en_din_i and rdy_din_o
# By monitoring their values simultaneously, we gain insights into how changes in one signal may affect the other and vice versa.
21 @CoverCross("top.en_din_i","top.rdy_din_o")
22 def handshake_cross(en_din_i, rdy_din_o):
23 pass
24# A sample_coverage(dut) coroutine runs continuously to sample and collect coverage data in particular sampling the cross coverage, defined earlier, at each rising edge of the clock signal.
25 async def sample_coverage(dut):
26 while True:
27 # Sample the cross coverage
28 handshake_cross(dut.en_din_i, dut.rdy_din_o)
29
30 # Wait for rising edge on clock
31 await RisingEdge(dut.CLK)
32
#These coverage points allow us to track and analyze the values of the DUT input data port din_i and DUT data output port dout_o signals, respectively. In the verification log it should be proof that the verification run detects at least once every possible 4 bit input and output data value in a range of 0-15.
33 @CoverPoint("top.din_i", # noqa F405
34 bins=[0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15]
35 )
36 def din_i_cover(din_i):
37 pass
38
39 @CoverPoint("top.dout_o", # noqa F405
40 bins=[0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15]
41 )
42
43 def dout_o_cover(dout_o):
44 pass
45
46 # The SimpleDUTDriver class is responsible for driving inputs to the din signal of the DUT.
47 class SimpleDUTDriver(BusDriver):
48 _signals = ['en_din_i', 'din_i', 'en_dout_i', 'rdy_din_o', 'dout_o', 'rdy_dout_o' ] # Define the list of signals to be driven
49
50 def __init__(self, dut, clock):
51 BusDriver.__init__(self, dut, None, dut.CLK) # Connect to the clock signal
52
53 @cocotb.coroutine
54 # The stimulus coroutine drives inputs to the DUT's din_i input port, as well as handles input side handshake control signals

55 async def stimulus(dut, stimulus_complete, stimulus_data, number_of_transfers ):
56 dut._log.info("Running stimulus...")
# initialize count variable to 0 ( count variable useful in observing FIFO accesses).The dut.en_din_i.value and dut.din_i.value are set to 0 initially too.
57 dut.en_din_i.value = 0
58 dut.din_i.value = 0
59 count = 0
60 # Drive some inputs
# for loop (lines 61-80) iterates number_of_transfers times, driving inputs to the DUT
61 for i in range(number_of_transfers):
62 dut.en_din_i.value = 0
63 dut.din_i.value = 0
# for each input data to send to DUT, there is a randomization of a delay before setting en_din_i to 1
# The loop generates a random value between 0 and 20 and waits for the corresponding number of rising edges of the clock signal.
64 for j in range(random.randint(0, 20)):
65 await RisingEdge(dut.CLK)
66 dut.en_din_i.value = 1
67# Updating the coverage point en_din_i_cover with the value of dut.en_din_i.
68 en_din_i_cover(dut.en_din_i.value)
# Updating the coverage cross handshake_cross with the values of dut.en_din_i and dut.rdy_din_o.
69 handshake_cross(dut.en_din_i.value, dut.rdy_din_o.value)
70 # Generating a random stimulus value of the input data and assigning it to dut.din_i
71 stimulus_value = random.randint(0, 15)
72 dut.din_i.value = stimulus_value
73 # Updating the coverage point din_i_cover with the stimulus value
74 din_i_cover(stimulus_value)
75 # Appending the stimulus value to the stimulus_data deque ( FIFO) and logging the value using cocotb.log.info
76 stimulus_data.append(stimulus_value)
77 count += 1 # Increment the variable
78 cocotb.log.info("Stimulus value: %d added in fifo on position %d ", stimulus_value, count) # Log the value
79 await RisingEdge(dut.CLK)
80
81 rdy_din_o_cover(dut.rdy_din_o.value)
82 handshake_cross(dut.en_din_i.value, dut.rdy_din_o.value)
83
84 if dut.rdy_din_o.value != 1:
85 await RisingEdge(dut.dut.rdy_din_o)
86 await FallingEdge(dut.dut.rdy_din_o)
87
88 rdy_din_o_cover(dut.rdy_din_o.value)
89 handshake_cross(dut.en_din_i.value, dut.rdy_din_o.value)
90 #After the loop completes, the stimulus is finalized
91 dut.en_din_i.value = 0
92 en_din_i_cover(dut.en_din_i.value)
93 handshake_cross(dut.en_din_i.value, dut.rdy_din_o.value)
94
95 dut.din_i.value = 0
96 await RisingEdge(dut.CLK)
97 # stimulus is complete, and the stimulus_complete event is set, signaling the completion of the stimulus
98 dut._log.info("Stimulus complete.")
99 stimulus_complete.set() # Set the stimulus_complete flag when stimulus is finished
100
101 @cocotb.coroutine
102 async def check_output(dut, stimulus_complete, stimulus_data, number_of_transfers):
# The check_output coroutine starts by logging an informational message to indicate that the output verification process is starting
103 dut._log.info("Checking output...")
# initializes the en_dout_i signal of the DUT to 0
104 dut.en_dout_i.value = 0
# initializes a counter variable, count, to keep track of the number of outputs processed.
105 count = 0
106
107 # Verify the output
# The verification process begins with a loop that iterates for the specified number of transfers (defined by the number_of_transfers variable). This loop is responsible for checking each output value against the expected value stored in the FIFO queue (stimulus_data).
108 for i in range(number_of_transfers):
# The loop checks if the stimulus generation process (stimulus_complete) has finished. If it has, the coroutine returns, indicating that the verification process is complete.
109 if stimulus_complete.is_set():
110 return # Exit the coroutine if stimulus is complete
111 if dut.rdy_dout_o.value == 0:
# The coroutine checks the readiness of the DUT's rdy_dout_o signal. It waits until the signal becomes high (1) before proceeding with the verification. This ensures that the DUT is ready to provide an output
112 await RisingEdge(dut.rdy_dout_o)
113 await RisingEdge(dut.CLK)
114 if dut.rdy_dout_o.value == 1:
# DUT has output data ready to send out. Here is randomized how many clock cycles DUT has to wait before it can dispense the data
115 for j in range(random.randint(0, 20)):
116 await RisingEdge(dut.CLK)
117 dut.en_dout_i.value = 1
# Retrieve the expected output value from the FIFO queue and the actual output value from the DUT (dout_o). The expected output is stored in the expected_output variable ( FIFO ), while the actual output is stored in the real_output variable
118 expected_output = stimulus_data.popleft() # Get the stimulus value from the FIFO queue
119 real_output = dut.dout_o.value
120
121 dout_o_cover(real_output)
122
# The count variable is incremented in line 123 to keep track of the number of outputs processed
123 count += 1 # Increment the variable
# logs an informational message indicating the expected output value and its position in the FIFO queue.
124 cocotb.log.info("Output expected value: %d removed fifo on position %d ", expected_output, count) # Log the value
# Checks if the expected output matches the actual output. If they don't match, an assertion error is raised, indicating an output mismatch. This ensures that the verification process fails if there is a discrepancy between the expected and actual output values
125 if expected_output != real_output:
126 cocotb.log.info("Matching: expected_output: %d to dout_o: %d ", expected_output, real_output) # Log the value
127 #warnings.warn(f"Output mismatch: Expected {expected_output}, {real_output}")
128 assert real_output == expected_output, f"Output mismatch: Expected {expected_output}, got {real_output}"
129 await RisingEdge(dut.CLK)
130 # Set the en_dout_i signal back to 0 and wait for another rising edge of the DUT's clock signal. This prepares the DUT for the next output
# The loop continues until all the specified number of transfers have been processed
131 dut.en_dout_i.value = 0
132 await RisingEdge(dut.CLK)
133 # Once the loop is complete, line 134 logs an informational message indicating that the output check has passed.
134 dut._log.info("Output check passed.")
135
136
137 @cocotb.test()
138 async def basic_count(dut):
139 # Set the random seed
140 #random.seed(42)
141
142 # generate a clock
143 cocotb.start_soon(Clock(dut.CLK, 1, units="ns").start())
144
145 # Call the sample_coverage coroutine to start sampling the cross coverage
146 cocotb.start_soon(sample_coverage(dut))
147
148 # Reset DUT
149 dut.RST_N.value = 1
150
151 # reset the module, wait 2 rising edges until we release reset
152 for _ in range(2):
153 await RisingEdge(dut.CLK)
154 dut.RST_N.value = 0
155
156 for _ in range(2):
157 await RisingEdge(dut.CLK)
158 dut.RST_N.value = 1
159
160 stimulus_complete = cocotb.triggers.Event() # Create an Event object to signal stimulus completion
161 stimulus_data = deque() # FIFO queue to store stimulus data
162 number_of_transfers = random.randint(32, 64)
163
164 cocotb.start_soon(stimulus(dut, stimulus_complete, stimulus_data, number_of_transfers))
165 #By using await check_output(dut), the test function will pause its execution at that point and resume only when the check_output coroutine has completed.
166 await check_output(dut, stimulus_complete, stimulus_data, number_of_transfers )
167
168 coverage_db.report_coverage(cocotb.log.info, bins=True)
169 coverage_file = os.path.join(os.getenv('RESULT_PATH', "./"), 'coverage.xml')
170 coverage_db.export_to_xml(filename=coverage_file)

SimpleDUT_hs_test.py functionality

The code begins by importing necessary modules and libraries for the implementation of a cocotb-based testbench. It includes modules for clock management, triggers, bus drivers, result handling, randomization, warnings, and coverage analysis.

Main test function: basic_count and SimpleDUTDriver

Lines 137-until the end of the file(line 170) present the basic_count test function, which includes the initialization, clock generation, reset control, stimulus generation, and output verification using the defined coroutines. Coverage reporting and exporting are performed at the end of the test.

Lines 47-52 define a bus driver class called SimpleDUTDriver responsible for driving signals to the DUT (Device Under Test).

coroutines for stimulus generation and output verification

The both coroutines (stimulus and check_output) are defined with the async def syntax, indicating that it can be paused and resumed asynchronously.

Also the both coroutines take the same four parameters each :

dut (representing the DUT instance),
stimulus_complete (an event object to signal stimulus completion),
stimulus_data (a deque object to store stimulus values), and
number_of_transfers (indicating the number of transfers to be performed)

number_of_transfers value is also randomized on line 162 in the range of 32 to 64: number_of_transfers = random.randint(32, 64))

asynchronous coroutine named stimulus

Lines 54-99 present an asynchronous coroutine named stimulus and here is what it does.

generates randomized stimulus values for two DUT input ports:

4 bit data din_i and
en_din_i part of corresponding handshake control for transfer input data ( din_i)

also it follows a handshake protocol by checking and ensuring the readiness of the rdy_din_o signal before driving inputs.

updates coverage points for various signals, and
logs the stimulus values.
updates coverage points(din_i and en_din_i ) and logs the stimulus values.

asynchronous coroutine named check_output

The check_output coroutine is responsible for verifying the correctness of the DUT's output by comparing it with the expected values stored in the FIFO queue. It also updates coverage points associated with the output signal and logs relevant output information for analysis and debugging purposes.

The verification process begins with a loop that iterates for the randomized number of transfers (defined by the number_of_transfers variable). This loop is responsible for checking each output value against the expected value stored in the FIFO queue (stimulus_data).

A waveform detail of the verification run

Simulation log file

rm -rf sim_build

make sim MODULE=SimpleDUT_hs_test TOPLEVEL=SimpleDUT_hs_test

make[1]: Entering directory '/< your path >/tests'

rm -f results.xml

make -f Makefile results.xml

make[2]: Entering directory '/< your path >/tests'

make[2]: Warning: File '/< your path >/tests/../hdl/SimpleDUT_hs.v' has modification time 9182 s in the future

mkdir -p sim_build

/usr/bin/iverilog -o sim_build/sim.vvp -D COCOTB_SIM=1 -s SimpleDUT_hs_test -f sim_build/cmds.f -g2012 /< your path >/tests/../hdl/or_gate.v /< your path >/tests/wrappers/or_test.v /< your path >/tests/wrappers/ifc_test.v /< your path >/tests/../hdl/ifc_or.v /< your path >/tests/../hdl/FIFO1.v /< your path >/tests/../hdl/FIFO2.v /< your path >/tests/../hdl/SimpleDUT.v /< your path >/tests/wrappers/SimpleDUT_test.v /< your path >/tests/../hdl/SimpleDUT_hs.v /< your path >/tests/wrappers/SimpleDUT_hs_test.v /< your path >/tests/../hdl/count_up.v /< your path >/tests/wrappers/count_up_test.v

rm -f results.xml

MODULE=SimpleDUT_hs_test TESTCASE= TOPLEVEL=SimpleDUT_hs_test TOPLEVEL_LANG=verilog \

/usr/bin/vvp -M /home/tilic/tomislav/cocoTB_tutorial/venv/lib/python3.11/site-packages/cocotb/libs -m libcocotbvpi_icarus sim_build/sim.vvp

-.--ns INFO gpi ..mbed/gpi_embed.cpp:105 in set_program_name_in_venv Using Python virtual environment interpreter at /home/tilic/tomislav/cocoTB_tutorial/venv/bin/python

-.--ns INFO gpi ../gpi/GpiCommon.cpp:101 in gpi_print_registered_impl VPI registered

0.00ns INFO cocotb Running on Icarus Verilog version 11.0 (stable)

0.00ns INFO cocotb Running tests with cocotb v1.8.0 from /home/tilic/tomislav/cocoTB_tutorial/venv/lib/python3.11/site-packages/cocotb

0.00ns INFO cocotb Seeding Python random module with 1687860737

0.00ns INFO cocotb.regression Found test SimpleDUT_hs_test.basic_count

0.00ns INFO cocotb.regression running basic_count (1/1)

3.00ns INFO cocotb.SimpleDUT_hs_test Running stimulus...

3.00ns INFO cocotb.SimpleDUT_hs_test Checking output...

7.00ns INFO cocotb Stimulus value: 7 added in fifo on position 1

19.00ns INFO cocotb Output expected value: 7 removed fifo on position 1

26.00ns INFO cocotb Stimulus value: 2 added in fifo on position 2

28.00ns INFO cocotb Output expected value: 2 removed fifo on position 2

35.00ns INFO cocotb Stimulus value: 12 added in fifo on position 3

47.00ns INFO cocotb Stimulus value: 9 added in fifo on position 4

51.00ns INFO cocotb Output expected value: 12 removed fifo on position 3

62.00ns INFO cocotb Stimulus value: 5 added in fifo on position 5

68.00ns INFO cocotb Output expected value: 9 removed fifo on position 4

71.00ns INFO cocotb Stimulus value: 9 added in fifo on position 6

77.00ns INFO cocotb Output expected value: 5 removed fifo on position 5

92.00ns INFO cocotb Stimulus value: 4 added in fifo on position 7

98.00ns INFO cocotb Output expected value: 9 removed fifo on position 6

102.00ns INFO cocotb Stimulus value: 8 added in fifo on position 8

118.00ns INFO cocotb Output expected value: 4 removed fifo on position 7

121.00ns INFO cocotb Output expected value: 8 removed fifo on position 8

135.00ns INFO cocotb Stimulus value: 0 added in fifo on position 9

138.00ns INFO cocotb Stimulus value: 1 added in fifo on position 10

144.00ns INFO cocotb Output expected value: 0 removed fifo on position 9

162.00ns INFO cocotb Stimulus value: 7 added in fifo on position 11

166.00ns INFO cocotb Output expected value: 1 removed fifo on position 10

171.00ns INFO cocotb Output expected value: 7 removed fifo on position 11

173.00ns INFO cocotb Stimulus value: 8 added in fifo on position 12

175.00ns INFO cocotb Stimulus value: 10 added in fifo on position 13

186.00ns INFO cocotb Output expected value: 8 removed fifo on position 12

193.00ns INFO cocotb Output expected value: 10 removed fifo on position 13

199.00ns INFO cocotb Stimulus value: 7 added in fifo on position 14

219.00ns INFO cocotb Stimulus value: 7 added in fifo on position 15

219.00ns INFO cocotb Output expected value: 7 removed fifo on position 14

232.00ns INFO cocotb Stimulus value: 11 added in fifo on position 16

237.00ns INFO cocotb Output expected value: 7 removed fifo on position 15

250.00ns INFO cocotb Stimulus value: 13 added in fifo on position 17

253.00ns INFO cocotb Output expected value: 11 removed fifo on position 16

263.00ns INFO cocotb Stimulus value: 0 added in fifo on position 18

274.00ns INFO cocotb Output expected value: 13 removed fifo on position 17

294.00ns INFO cocotb Stimulus value: 13 added in fifo on position 19

296.00ns INFO cocotb Output expected value: 0 removed fifo on position 18

304.00ns INFO cocotb Stimulus value: 9 added in fifo on position 20

311.00ns INFO cocotb Output expected value: 13 removed fifo on position 19

313.00ns INFO cocotb Stimulus value: 12 added in fifo on position 21

317.00ns INFO cocotb Output expected value: 9 removed fifo on position 20

322.00ns INFO cocotb Output expected value: 12 removed fifo on position 21

335.00ns INFO cocotb Stimulus value: 13 added in fifo on position 22

339.00ns INFO cocotb Output expected value: 13 removed fifo on position 22

355.00ns INFO cocotb Stimulus value: 9 added in fifo on position 23

369.00ns INFO cocotb Output expected value: 9 removed fifo on position 23

371.00ns INFO cocotb Stimulus value: 2 added in fifo on position 24

376.00ns INFO cocotb Stimulus value: 7 added in fifo on position 25

376.00ns INFO cocotb Output expected value: 2 removed fifo on position 24

387.00ns INFO cocotb Output expected value: 7 removed fifo on position 25

391.00ns INFO cocotb Stimulus value: 2 added in fifo on position 26

407.00ns INFO cocotb Stimulus value: 9 added in fifo on position 27

411.00ns INFO cocotb Output expected value: 2 removed fifo on position 26

413.00ns INFO cocotb Output expected value: 9 removed fifo on position 27

418.00ns INFO cocotb Stimulus value: 3 added in fifo on position 28

427.00ns INFO cocotb Stimulus value: 4 added in fifo on position 29

431.00ns INFO cocotb Output expected value: 3 removed fifo on position 28

433.00ns INFO cocotb Output expected value: 4 removed fifo on position 29

436.00ns INFO cocotb Stimulus value: 15 added in fifo on position 30

449.00ns INFO cocotb Output expected value: 15 removed fifo on position 30

454.00ns INFO cocotb Stimulus value: 13 added in fifo on position 31

464.00ns INFO cocotb Stimulus value: 7 added in fifo on position 32

470.00ns INFO cocotb Output expected value: 13 removed fifo on position 31

482.00ns INFO cocotb Output expected value: 7 removed fifo on position 32

489.00ns INFO cocotb Stimulus value: 1 added in fifo on position 33

494.00ns INFO cocotb Stimulus value: 9 added in fifo on position 34

498.00ns INFO cocotb Output expected value: 1 removed fifo on position 33

513.00ns INFO cocotb Output expected value: 9 removed fifo on position 34

515.00ns INFO cocotb Stimulus value: 8 added in fifo on position 35

518.00ns INFO cocotb Output expected value: 8 removed fifo on position 35

519.00ns INFO cocotb Stimulus value: 8 added in fifo on position 36

521.00ns INFO cocotb.SimpleDUT_hs_test Stimulus complete.

541.00ns INFO cocotb Output expected value: 8 removed fifo on position 36

543.00ns INFO cocotb.SimpleDUT_hs_test Output check passed.

543.00ns INFO cocotb top : <cocotb_coverage.coverage.CoverItem object at 0x7fcc4ce2a8d0>, coverage=32, size=36

543.00ns INFO cocotb top.din_i : ( ASICStoic comment: each of 16 values of DUT 4 bit input din_i is exercised in the test: there no BIN 0-15 = 0) <cocotb_coverage.coverage.CoverPoint object at 0x7fcc4cdfaed0>, coverage=14, size=16

543.00ns INFO cocotb BIN 0 : 2

543.00ns INFO cocotb BIN 1 : 2

543.00ns INFO cocotb BIN 2 : 3

543.00ns INFO cocotb BIN 3 : 1

543.00ns INFO cocotb BIN 4 : 2

543.00ns INFO cocotb BIN 5 : 1

543.00ns INFO cocotb BIN 6 : 1

543.00ns INFO cocotb BIN 7 : 6

543.00ns INFO cocotb BIN 8 : 4

543.00ns INFO cocotb BIN 9 : 6

543.00ns INFO cocotb BIN 10 : 1

543.00ns INFO cocotb BIN 11 : 1

543.00ns INFO cocotb BIN 12 : 2

543.00ns INFO cocotb BIN 13 : 4

543.00ns INFO cocotb BIN 14 : 1

543.00ns INFO cocotb BIN 15 : 1

543.00ns INFO cocotb top.dout_o : ( ASICStoic comment: each of 16 values of DUT 4 bit output dout_o is exercised in the test: there no BIN 0-15 = 0)<cocotb_coverage.coverage.CoverPoint object at 0x7fcc4cdfab10>, coverage=14, size=16

543.00ns INFO cocotb BIN 0 : 2

543.00ns INFO cocotb BIN 1 : 2

543.00ns INFO cocotb BIN 2 : 3

543.00ns INFO cocotb BIN 3 : 1

543.00ns INFO cocotb BIN 4 : 2

543.00ns INFO cocotb BIN 5 : 1

543.00ns INFO cocotb BIN 6 : 1

543.00ns INFO cocotb BIN 7 : 6

543.00ns INFO cocotb BIN 8 : 4

543.00ns INFO cocotb BIN 9 : 6

543.00ns INFO cocotb BIN 10 : 1

543.00ns INFO cocotb BIN 11 : 1

543.00ns INFO cocotb BIN 12 : 2

543.00ns INFO cocotb BIN 13 : 4

543.00ns INFO cocotb BIN 14 : 1

543.00ns INFO cocotb BIN 15 : 1

543.00ns INFO cocotb top.en_din_i : <cocotb_coverage.coverage.CoverPoint object at 0x7fcc4cdfa9d0>, coverage=2, size=2

543.00ns INFO cocotb BIN 0 : 36

543.00ns INFO cocotb BIN 1 : 1

543.00ns INFO cocotb top.rdy_din_o : <cocotb_coverage.coverage.CoverPoint object at 0x7fcc4e96e150>, coverage=2, size=2

543.00ns INFO cocotb BIN 0 : 36

543.00ns INFO cocotb BIN 1 : 36

543.00ns INFO cocotb.regression basic_count passed

543.00ns INFO cocotb.regression ***************************************************************************************

** TEST STATUS SIM TIME (ns) REAL TIME (s) RATIO (ns/s) **

***************************************************************************************

** SimpleDUT_hs_test.basic_count PASS 543.00 0.15 3516.28 **

***************************************************************************************

** TESTS=1 PASS=1 FAIL=0 SKIP=0 543.00 0.25 2138.51 **

***************************************************************************************

VCD info: dumpfile SimpleDUT_hs.vcd opened for output.

ASIC Stoic

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Wednesday, June 28, 2023

Introduction

Here is a source code of the blog post files

SimpleDUT_hs.v (The DUT)

A Python/CoCoTB testbench for the DUT verification integrated with a self-checking/randomized test ( with some coverage reporting capability): SimpleDUT_hs_test.py

SimpleDUT_hs_test.py functionality

Main test function: basic_count and SimpleDUTDriver

coroutines for stimulus generation and output verification

asynchronous coroutine named stimulus

asynchronous coroutine named check_output

A waveform detail of the verification run

Simulation log file