ASIC Stoic: Oct 14, 2019

Part #3: CMOS Analog Design Basics: an example of

transistor sizing when using the first time new techno

( e.g. 1um ) and we need NMOS transistor in saturation

with ID=400uA and VGS bias is 1.5V

Hi,

As a friendly reminder in the first document of the series: “CMOS Analog Design Basics: an example
of transistor sizing when using the first time new techno ( e.g. 1um ) and we need NMOS transistor
in saturation with ID=400uA and VGS bias is 1.5V” as a title said our goal was to use these input data:

1μ techo ( here is a Spice models of CMOS transistors ):

Alim. of Vdd =5V
Assuming bias VGS=1.5V

To achieve ID=400μA .

And in the past, for this purpose I have chosen the following schematic:

For the schematic I calculated and adjusted in simulation the NMOS transistor sizing W/L=17 and
LTspice simulation showed: IDS = approx. 398 μA and VDSsat= approx. 711mV.

And in the second document of the series: “PART#2: CMOS Analog Design Basics: an example of
transistor sizing when using the first time new techno ( e.g. 1um ) and we need NMOS transistor in
saturation with ID=400uA and VGS bias is 1.5V” I replaced R1 with a diode connected PMOS
( and calculated it’s sizing W/L ):

Now I would like to bias transistor M1 with a necessary bias of VGS1=1.5V and for that
I am assuming that I have on my disposal a current source of 20uA.

Here is a schematic ( “topology”) I am planning to use:

The basic idea of achieving transistor M1 biasing with VGS1=1.5V is to choose VSG4 of PMOS
transistor M4 in such a way that VDD - VSG4 = 1.5V

This is transistor equations ( a MOSFET transistor in saturation ) used for the sizing calculation:

Note*: As in previous schematics I decided to keep all MOSFET transistor length to one fixed
value: L=2um.

Also I need to take care that M3 stays in saturation when VGS1=1.5 V because VGS1= VDS3sat and
to do this I need to provide that VDS3sat > VGS3 -VTO(nmos).

Since from Spice model of my NMOS transistor I know that

=> 1.5V > VGS3 - 0.8V

=> 2.3V > VGS3

Since VGS5=VGS3 , this means that I cannot choose sizing of NMOS transistor M5 to have
VGS3 > 2.3V so let me choose a convenient value VGS3=1.05 V.

Note* I have chosen VGS3=1.05 V because of my previous knowledge about this technology
mainly summarised from the following table:

To simplify our calculation let’s say that in our current mirror transistors M3 and M5 are equivalent in
size and also that we want to adjust our topology to have ID3=ID5=I1=20uA.

Also let’s temporary simplify our topology replacing transistor M4 with a resistor R of unknown size
for the moment:

By doing simulation using parameter R1 “sweep” we will find value of R1 ( r1 approx. 174K ) to give
us VGS1=1.5V, keeping ID3=20uA.

And really when for R1=174K we are getting biasing voltage VGS1=1.5V while keeping currents
equal: I1=ID3=ID5=IR1=20uA:

The last step is replacing resistor R1 with PMOS and calculation of the size of the PMOS was already
explained in previous blog post: “Part #2: CMOS Analog Design Basics: an example of transistor
sizing when using the first time new techno ( e.g. 1um ) and we need NMOS transistor in saturation
with ID=400uA and VGS bias is 1.5V”

But I made an assumption that I could achieve VGS1= 1.5V by having ID3 = ID4=10uA .
Let’s see if it is possible to size PMOS transistor M4 to do this.

By doing simulation using parameter PMOS transistor M4 W “sweep” it is clear this is impossible:
even for a small value of W=2u VGS1 is more than 2.9V:

So I decided to choose a small value for PMOS transistor W=4u and then to “sweep”
NMOS transistor M3 W for a value large enough to increase current ID3=ID4 so VGS1
can fall to the desired value VGS1=1.5V: