A use case of: UVM verification environment universal template

 Verilog RTL verification

A use case of: UVM verification environment universal template

Using UVM verification environment universal template as a starting point for full verification of a simple RTL Digital Design Under Test (DUT)

In this blog post there is a source code of all UVM verification environment files to use in verification of a simple RTL Digital Design Under Test (DUT). The assembly of files of  the UVM verification is based on UVM verification environment universal template as described in the previous blog post: https://asicstoic.blogspot.com/2023/06/uvm-verification-environment-universal.html  .

UVM verification environment  architecture

For UVM verification  of any DUT what  we need to think about is an architecture so our architecture will contain files organized in a  System Verilog UVM hierarchy as described in previously showed  block diagram 

• top testbench module :  testbench.sv

• Design file 

• DUT.sv 

• UVM verification infrastructure files

•  Interface.sv ( SystemVerilog interface of a desired DUT ) 

• UVM verification classes ( one class per file and  per  UVM block in previously presented block diagram) :

• test class (COMPONENT class, test.sv)

• environment class (COMPONENT class, env.sv) 

• scoreboard  class (COMPONENT class, scoreboard.sv)

• agent class ( COMPONENT class, agent.sv)  

• driver (COMPONENT class, driver.sv) 

• monitor (COMPONENT class, monitor.sv)  

• sequencer (COMPONENT class, sequencer.sv) 

• sequence/sequence item ( two OBJECT classes in one file:  sequence.sv)

DUT 

module SimpleDUT (     input clk,     input reset,      input [3:0] din_i,     output [3:0] dout_o );     // Logic for the DUT     assign dout_o = din_i; endmodule

Interface

interface SimpleDUT_interface(input logic clock);   logic reset;   logic [3:0] din_i, dout_o; endinterface: SimpleDUT_interface

 testbench.sv ( top testbench module )

`timescale 1ns/1ns // This is where the basic UVM necessary classes are included that we need to get started with our top module. // The first thing, whenever you start with a UVM test bench, you need to define some UVM based packages so we need to import them here using  this  basic syntax import uvm_pkg::*; // we also need to include some UVM macros `include "uvm_macros.svh" //-------------------------------------------------------- //Include Files //-------------------------------------------------------- // The way we include the classes in the top testbench is that the order of the included classes is very important. // The first class that you are going to use should be the first one included and so on. // e.g. that is the reason why we start with sequence item class etc.etc. `include "interface.sv" `include "sequence_item.sv" `include "sequence.sv" `include "sequencer.sv" `include "driver.sv" `include "monitor.sv" `include "agent.sv" `include "scoreboard.sv" `include "env.sv" `include "test.sv" module top; // the clock for DUT is generated  from the top testbench module so let's declare a signal clock here logic clock;     SimpleDUT_interface intf(.clock(clock));     SimpleDUT dut(     .clk(intf.clock),     .reset(intf.reset),     .din_i(intf.din_i),     .dout_o(intf.dout_o) ); //--------------------------------------------------------   //Interface Setting   //--------------------------------------------------------   initial begin // In SystemVerilog, the uvm_config_db is a utility provided by the Universal Verification Methodology (UVM) library. It allows you to set configuration values in a centralized database that can be accessed by different components of your testbench // uvm_config_db is the class that provides the configuration database functionality in UVM // In the given example, the uvm_config_db::set call sets the configuration value "vif" with the value intf (an instance of SimpleDUT_interface) in the global context for all instances in the hierarchy. This allows other components of the testbench to access and use this configuration value when needed. /* #(virtual SimpleDUT_interface): This is a type parameter passed to the uvm_config_db class, specifying the data type of the configuration value. In this case, it is a virtual interface type called SimpleDUT_interface. set: This is a static method of the uvm_config_db class used to set a configuration value in the database. null: This represents the context in which the configuration value is being set. In this case, it is set to null, indicating a global context. "*": This is the hierarchical path pattern specifying the scope at which the configuration value is applicable. In this case, "*" indicates that the configuration applies to all instances in the hierarchy. "vif": This is the name of the configuration field being set. It is a user-defined identifier that represents a specific configuration parameter or object in the database. intf: This is the value being set for the configuration field "vif". It represents an instance of the SimpleDUT_interface virtual interface. */     uvm_config_db #(virtual SimpleDUT_interface)::set(null, "*", "vif", intf );     //-- Refer: https://www.synopsys.com/content/dam/synopsys/services/whitepapers/hierarchical-testbench-configuration-using-uvm.pdf   end // The last thing to add  in our top testbench  is:  start the test  and that is done by calling  run test task in. // The top module should take care of our test so when you reach this stage. //Start The Test   //--------------------------------------------------------   initial begin // we need to pass our test name inside this so our test name is "SimpleDUT_test" // we can also pass this from a parameter of through command     run_test("SimpleDUT_test");   end     //--------------------------------------------------------   //Clock Generation   //-------------------------------------------------------- // Since the clock for DUT is generated  from the top testbench module , let's generate the clock here   initial begin     clock = 0;     #5;     forever begin       clock = ~clock;       #2;     end   end   //--------------------------------------------------------   //Maximum Simulation Time   //-------------------------------------------------------- // let's also keep a safety check which terminates our simulation if a given number of clock Cycles X exceeds so we will keep it to maybe 5000ns   initial begin     #5000;     $display("Sorry! Ran out of clock cycles!");     $finish();   end       //--------------------------------------------------------   //Generate Waveforms   //--------------------------------------------------------   // if you want to see the waveforms you can also use the dump file  command to  tell the simulator to dump variable values so that   // you can inspect  the waveforms after verification/simulation   initial begin     $dumpfile("d.vcd");     $dumpvars();   end   endmodule: top

UVM Test Component template

// let's create a new class in a file named test.sv // we can start with naming our class SimpleDUT_test. // SimpleDUT_test   extends uvm_test class //COMPONENT class class SimpleDUT_test extends uvm_test;   // first thing we need to do in a class   // is declare the necessary macros that will help it   // register everything with the UVM classes   // so we need to call this macro called `uvm_component_utils   // and we need to pass the same name of the class that we are going to use   // and that is SimpleDUT_test   `uvm_component_utils(SimpleDUT_test)   //  second thing we need to do is write a Constructor   //  start with: function new();   //                    endfunction   // inside brackets of new() two parameters:  first  string name is equal to the   // name of the class( alu_test) and then we also need to write // uvm_component parent // Finally basic constructor for UVM classes is: // function new(string name = "SimpleDUT_test", uvm_component parent); //    super.new(name, parent); // endfunction: new // also keep some display statement so that it becomes easier to debug //  we will use the default `uvm_info macro that UVM already has // it has like three parameters first is the tag of the comment that we want to give(  we can just give a // TEST_CLASS and then we can also use a // just some comment that we want to pass when  inside this Constructor // ( "Inside Constructor!") // and then verbosity level for example UVM_HIGH           //--------------------------------------------------------   // Constructor   //--------------------------------------------------------   function new(string name = "SimpleDUT_test", uvm_component parent);     super.new(name, parent);     `uvm_info("TEST_CLASS", "Inside Constructor!", UVM_HIGH)   endfunction: new   //and now we need to write the build phase so   // we do that by using function void   //--------------------------------------------------------   // Build Phase   //--------------------------------------------------------   function void build_phase(uvm_phase phase);     super.build_phase(phase);     `uvm_info("TEST_CLASS", "Build Phase!", UVM_HIGH)       endfunction: build_phase // Next is  connect phase which is same similar to build phase // but we'll just change the syntax //--------------------------------------------------------   //Connect Phase   //--------------------------------------------------------   function void connect_phase(uvm_phase phase);     super.connect_phase(phase);     `uvm_info("TEST_CLASS", "Connect Phase!", UVM_HIGH)   endfunction: connect_phase // we also need to write a run phase. There are a lot of phases in a UVM but // these three are the main phases  with which // our SimplDUT could be verified easily // all the other phases are functions while only the run phase is a task because // run phase can consume time //--------------------------------------------------------   //Run Phase   //--------------------------------------------------------   task run_phase (uvm_phase phase);     super.run_phase(phase);     `uvm_info("TEST_CLASS", "Run Phase!", UVM_HIGH)   endtask: run_phase endclass: SimpleDUT_test

UVM Test Component ( final version based on  UVM Test Component template ) 

class SimpleDUT_test extends uvm_test;   `uvm_component_utils(SimpleDUT_test) // according to our block diagram the test component // will contain environment class environment class will contain agent agent will contain driver Monitor and // sequencer so we need to write the code accordingly // Here in test class let's instantiate an SimpleDUT_env object named env and initialize it using the create method, passing a unique name and the current test class as the parent. This allows the test class to interact with and control the instantiated environment during test execution. // 1. change of test class based on test class template:  so let's instantiate the // environment class inside the test SimpleDUT_env env // This is just the instantiation // This line declares a variable named env of type SimpleDUT__env. This variable will be used to hold an instance of the SimpleDUT_env class, which represents the test environment.   SimpleDUT_env env; // 4. change of test class based on test class template:  // In order to start our sequences in the run phase //  we need the sequence instances and here we  have two sequences that we created: one is the // base sequence and another one is the test sequence so let's just create their handles // Instantiation two sequences   SimpleDUT_base_sequence reset_seq;   SimpleDUT_test_sequence test_seq;           //--------------------------------------------------------   // Constructor   //--------------------------------------------------------   function new(string name = "SimpleDUT_test", uvm_component parent);     super.new(name, parent);     `uvm_info("TEST_CLASS", "Inside Constructor!", UVM_HIGH)   endfunction: new   //--------------------------------------------------------   // Build Phase   //--------------------------------------------------------   function void build_phase(uvm_phase phase);     super.build_phase(phase);     `uvm_info("TEST_CLASS", "Build Phase!", UVM_HIGH) // 2. change of test class based on test class template: and we also need to create env inside the build method( env = SimpleDUT_env::type_id::create("env", this);) // This line creates an instance of the SimpleDUT_env class using the create method // this is a component class so for its creation  we need to pass two parameters:  one is the "env" a name itself // so whatever we want the env to be called to be known in the testbench and // you also need to pass "this" as a parameter "this" will specify who is the parent of the environment // so it's just like SimpleDUT_test contains the environment class // SimpleDUT_env::type_id is used to obtain the type identifier of the SimpleDUT_env class. The type identifier is a unique identifier generated by the UVM framework for each class. It allows for dynamic object creation and type checking. // The create method takes two arguments: // "env": This is the desired name for the created object. It is passed as a string. // "this": This is a reference to the current object or component. In this case, it refers to the test class where this code is executed. // The "this" pointer is used to specify the parent of the created object, which helps establish the hierarchical relationship between components in the UVM environment.     env = SimpleDUT_env::type_id::create("env", this);       endfunction: build_phase //--------------------------------------------------------   //Connect Phase   //--------------------------------------------------------   function void connect_phase(uvm_phase phase);     super.connect_phase(phase);     `uvm_info("TEST_CLASS", "Connect Phase!", UVM_HIGH)   endfunction: connect_phase   //--------------------------------------------------------   //Run Phase   //--------------------------------------------------------   task run_phase (uvm_phase phase);     super.run_phase(phase);     `uvm_info("TEST_CLASS", "Run Phase!", UVM_HIGH)     // 3. change of test class based on test class template:  // run phase of the test class will start the sequences that it wants to run. // To do that one important thing test class we need to do in test class is // we need to say that:  hey I'm going to run my test // and for that we use the phase.raise_objection. // Also  after we are done // with the test we also need to phase.drop_objection so that the test can end.       phase.raise_objection(this); // 5. change of test class based on test class template: // When starting  my reset sequence on sequencer first we // specify a path of that sequencer, something like env agent sequencer // ( env.agnt.seqr) because our sequence  is lying inside the agent which is lying inside the environment. // So we specify that path over here so what this will do is to  start this reset sequence on this // sequencer which is lying inside this agent which is in turn lying inside this environment. // This is done  because there can be multiple environments and multiple agents and also multiple sequencers so we are specifying which sequencer we want to run our sequence on     //reset_seq     // Constructing the reset sequence     reset_seq = SimpleDUT_base_sequence::type_id::create("reset_seq");     // Starting the reset sequence on the sequencer on path env.agnt.seqr     reset_seq.start(env.agnt.seqr);     //  this extra delay if  we are not the back to back transactions     #10;     repeat(100) begin       //test_seq       // Constructing the test sequence        test_seq = SimpleDUT_test_sequence::type_id::create("test_seq");       // Starting the test sequence on the sequencer on path env.agnt.seqr       test_seq.start(env.agnt.seqr);       #10;     end         phase.drop_objection(this);   endtask: run_phase

Environment class/other COMPONENT classes templates

 Let's create the environment class template which will be same as the test class template ( and in the same fashion all other necessary COMPONENT classes templates ) 

• As a friendly reminder the  environment class template  will have  instances of agent and scoreboard classes template instances  as it is planned in our UVM verification infrastructure architecture 

class SimpleDUT_env extends uvm_test;   `uvm_component_utils(SimpleDUT_env)   //--------------------------------------------------------   //Constructor   //--------------------------------------------------------   function new(string name = "SimpleDUT_env", uvm_component parent);     super.new(name, parent);     `uvm_info("ENV_CLASS", "Inside Constructor!", UVM_HIGH)   endfunction: new   //--------------------------------------------------------   //Build Phase   //--------------------------------------------------------   function void build_phase(uvm_phase phase);     super.build_phase(phase);     `uvm_info("ENV_CLASS", "Build Phase!", UVM_HIGH)   endfunction: build_phase     //--------------------------------------------------------   //Connect Phase   //--------------------------------------------------------   function void connect_phase(uvm_phase phase);     super.connect_phase(phase);     `uvm_info("ENV_CLASS", "Connect Phase!", UVM_HIGH)   endfunction: connect_phase     //--------------------------------------------------------   //Run Phase   //--------------------------------------------------------   task run_phase (uvm_phase phase);     super.run_phase(phase);     `uvm_info("ENV_CLASS", "Run Phase!", UVM_HIGH)   // Logic     endtask: run_phase endclass: SimpleDUT_env

Environment class ( final version and based on Environment class template ) 

class SimpleDUT_env extends uvm_test;   `uvm_component_utils(SimpleDUT_env) // according to our block diagram the  environment class will contain agent, then  agent will contain driver monitor and sequencer so we need to write the code accordingly // Here in environment class, let's instantiate a SimpleDUT_agent object named agnt and initialize it using the create method, passing a unique name and the current environment  class as the parent. This allows the  environment class to interact with and control the instantiated agent during test execution. // 1. change of environment class based on environment class template:  so let's instantiate the // agent class inside the environment (SimpleDUT_agent agnt) // This is just the instantiation // This line declares a variable named env of type SimpleDUT_agent. This variable will be used to hold an instance of the SimpleDUT__agent class, which represents the agent in the environment. SimpleDUT_agent agnt; // 4. change of environment class based on environment class template: // In order to connect monitor and  scoreboard we will always go to a higher component then these two. // Since agent and scoreboard lie on the same hierarchy while driver and monitor and sequencer lie inside the agent so now we need to go up a hierarchy above agent and scoreboard which is the environment. // In  the environment we can connect those ports in the connect phase of environment: // To connect the scoreboard later we need to instantiate it here SimpleDUT_scoreboard scb;   //--------------------------------------------------------   //Constructor   //--------------------------------------------------------   function new(string name = "SimpleDUT_env", uvm_component parent);     super.new(name, parent);     `uvm_info("ENV_CLASS", "Inside Constructor!", UVM_HIGH)   endfunction: new   //--------------------------------------------------------   //Build Phase   //--------------------------------------------------------   function void build_phase(uvm_phase phase);     super.build_phase(phase);     `uvm_info("ENV_CLASS", "Build Phase!", UVM_HIGH) // 2. change of environment class based on environment class template: // we also need to create an agent inside the build method( agnt = SimpleDUT_agent::type_id::create("agnt", this);) // This line creates an instance of the agent_env class using the create method // this is a component class we need to pass two parameters:  one is the "agnt" a name itself // so whatever we want the agnt to be called to be known as in the testbench and // we also need to pass "this" as a parameter this will specify who is the parent of agent // so here is SimpleDUT_env contains the agent class // SimpleDUT_agent::type_id is used to obtain the type identifier of the SimpleDUT_env class. The type identifier is a unique identifier generated by the UVM framework for each class. It allows for dynamic object creation and type checking. // The create method takes two arguments: // "agnt": This is the desired name for the created object. It is passed as a string.this: This is a reference to the current object or component. In this case, it refers to the test class where this code is executed. // The "this" pointer is used to specify the parent of the created object, which helps establish the hierarchical relationship between components in the UVM environment. agnt = SimpleDUT_agent::type_id::create("agnt", this); // 5. change of environment class based on environment class template: // same as 2. Change, do  the same for scoreboard scb = SimpleDUT_scoreboard::type_id::create("scb", this);   endfunction: build_phase     //--------------------------------------------------------   //Connect Phase   //--------------------------------------------------------   function void connect_phase(uvm_phase phase);     super.connect_phase(phase);     `uvm_info("ENV_CLASS", "Connect Phase!", UVM_HIGH) // 3. change of environment class based on environment class template: // Since we don't have the monitor handle over here in env.sv // we need to access it through agent:  agnt.mon.monitor_port.connect // and this is how we connect monitor port and scoreboard port. // Our monitor will monitor the items or sample the items and then  send items to // scoreboard through the port and scoreboard will do something with it. // To connect the scoreboard here,   we need to instantiate it before     agnt.mon.monitor_port.connect(scb.scoreboard_port);   endfunction: connect_phase     //--------------------------------------------------------   //Run Phase   //--------------------------------------------------------   task run_phase (uvm_phase phase);     super.run_phase(phase);     `uvm_info("ENV_CLASS", "Run Phase!", UVM_HIGH)   // Logic     endtask: run_phase endclass: SimpleDUT_env

 

Agent class template ( once more a Component class ) 

Let's create the agent class template which will be same as the environment and test class templates ( and in the same fashion all other necessary COMPONENT classes ) 

• The agent class template  will have  three instances  class templates:  driver sequencer and monitor

class SimpleDUT_agent extends uvm_agent;   `uvm_component_utils(SimpleDUT_agent)     //--------------------------------------------------------   //Constructor   //--------------------------------------------------------   function new(string name = "SimpleDUT_agent", uvm_component parent);     super.new(name, parent);     `uvm_info("AGENT_CLASS", "Inside Constructor!", UVM_HIGH)   endfunction: new     //--------------------------------------------------------   //Build Phase   //--------------------------------------------------------   function void build_phase(uvm_phase phase);     super.build_phase(phase);     `uvm_info("AGENT_CLASS", "Build Phase!", UVM_HIGH)   endfunction: build_phase     //--------------------------------------------------------   //Connect Phase   //--------------------------------------------------------   function void connect_phase(uvm_phase phase);     super.connect_phase(phase);     `uvm_info("AGENT_CLASS", "Connect Phase!", UVM_HIGH)   endfunction: connect_phase     //--------------------------------------------------------   //Run Phase   //--------------------------------------------------------   task run_phase (uvm_phase phase);     super.run_phase(phase);     `uvm_info("AGENT_CLASS", "Run Phase!", UVM_HIGH)   // Logic     endtask: run_phase endclass: SimpleDUT_agent

Agent class ( final version and based on the Agent class template )

class SimpleDUT_agent extends uvm_agent;   `uvm_component_utils(SimpleDUT_agent) // according to our block diagram the agent will contain driver, monitor and sequencer so we need to write the code accordingly // Here in agent class, let's instantiate a driver (SimpleDUT_driver),  a monitor (SimpleDUT_monitor) and sequencer (SimpleDUT_sequencer) objects named accordingly: drv, mon and seqr. As before we need to initialize all three using the create method, passing the unique names and the current agent  class as the parent. This allows the  agent class to interact with and control the instantiated driver, monitor and sequencer  during the test execution. // 1. change of agent class based on agent class template:   // Let's instantiate the // driver, monitor and sequencer classes inside the agent class.   SimpleDUT_driver    drv;   SimpleDUT_monitor   mon;   SimpleDUT_sequencer seqr;     //--------------------------------------------------------   //Constructor   //--------------------------------------------------------   function new(string name = "SimpleDUT_agent", uvm_component parent);     super.new(name, parent);     `uvm_info("AGENT_CLASS", "Inside Constructor!", UVM_HIGH)   endfunction: new     //--------------------------------------------------------   //Build Phase   //--------------------------------------------------------   function void build_phase(uvm_phase phase);     super.build_phase(phase);     `uvm_info("AGENT_CLASS", "Build Phase!", UVM_HIGH) // 2. change of agent class based on the agent class template:  // we also need to create the driver, monitor and sequencer inside the build method     drv = SimpleDUT_driver::type_id::create("drv", this);     mon = SimpleDUT_monitor::type_id::create("mon", this);     seqr = SimpleDUT_sequencer::type_id::create("seqr", this);   endfunction: build_phase     //--------------------------------------------------------   //Connect Phase   //--------------------------------------------------------   function void connect_phase(uvm_phase phase);     super.connect_phase(phase);     `uvm_info("AGENT_CLASS", "Connect Phase!", UVM_HIGH) // 3. change of agent class based on the agent class template: // In the connect phase we need to connect the sequence item ports of driver and sequencer. This is required // to exchange the transactions. // We want to connect drivers port to sequencers port (sequence_item_export) // These are the ports ( e.g. seq_item_port) that are by default defined inside the driver and  // sequencer class so this is how we just connect them. // They are used to exchange  transactions between  sequencer and driver ( here we have a hand-shake between sequencer and driver) drv.seq_item_port.connect(seqr.seq_item_export);   endfunction: connect_phase     //--------------------------------------------------------   //Run Phase   //--------------------------------------------------------   task run_phase (uvm_phase phase);     super.run_phase(phase);     `uvm_info("AGENT_CLASS", "Run Phase!", UVM_HIGH)      endtask: run_phase endclass: SimpleDUT_agent

 

Driver class  template ( one more Component class )

Note: driver class is a parameterized class so we need to pass the name of the sequence item class that we are going to use 

• we haven't created the sequence item class but I know the name of it will be: SimpleDUT_sequence_item)

• e.g. class SimpleDUT_driver extends uvm_driver#(SimpleDUT_sequence_item);

The driver knows what type of sequence item that we are going to drive on the sequencer and that is why we pass this as a parameter 

// Note: driver class is a parameterized class so we need to pass the name of the sequence item class that we are going to use // we haven't created the sequence item class but I know the name of it will be SimpleDUT_sequence_item)   class SimpleDUT_driver extends uvm_driver#(SimpleDUT_sequence_item);   `uvm_component_utils(SimpleDUT_driver)       //--------------------------------------------------------   //Constructor   //--------------------------------------------------------   function new(string name = "SimpleDUT_driver", uvm_component parent);     super.new(name, parent);     `uvm_info("DRIVER_CLASS", "Inside Constructor!", UVM_HIGH)   endfunction: new     //--------------------------------------------------------   //Build Phase   //--------------------------------------------------------   function void build_phase(uvm_phase phase);     super.build_phase(phase);     `uvm_info("DRIVER_CLASS", "Build Phase!", UVM_HIGH)   endfunction: build_phase     //--------------------------------------------------------   //Connect Phase   //--------------------------------------------------------   function void connect_phase(uvm_phase phase);     super.connect_phase(phase);     `uvm_info("DRIVER_CLASS", "Connect Phase!", UVM_HIGH)   endfunction: connect_phase     //--------------------------------------------------------   //Run Phase   //--------------------------------------------------------   task run_phase (uvm_phase phase);     super.run_phase(phase);     `uvm_info("DRIVER_CLASS", "Run Phase!", UVM_HIGH)   // Logic     endtask: run_phase endclass: SimpleDUT_driver

Driver class(final solution based of the Driver class template )

class SimpleDUT_driver extends uvm_driver#(SimpleDUT_sequence_item);   `uvm_component_utils(SimpleDUT_driver) //2. driver class template change :   // Now when we access that vif from the uvm_config_db. // Also  we want to copy or use a name that we // can use throughout the driver for that class. // We can use “vif” so we do need a handle for this // so we do need to declare it in the class somewhere here. // Finally what we declare is a virtual SimpleDUT_interface and the handle would be // “vif”. Now we know that this is virtual interface inside the driver virtual SimpleDUT_interface vif; //3. driver class template change  :  // Here we are moving on  to update  of the Run phase of the driver // which is the most important phase in the driver. // But first:  the thing we need to do first is to  declare the handle to the item that we are going  // to use in the driver, and that is SimpleDUT_sequence_item SimpleDUT_sequence_item item;   //--------------------------------------------------------   //Constructor   //--------------------------------------------------------   function new(string name = "SimpleDUT_driver", uvm_component parent);     super.new(name, parent);     `uvm_info("DRIVER_CLASS", "Inside Constructor!", UVM_HIGH)   endfunction: new   //--------------------------------------------------------   //Build Phase   //--------------------------------------------------------   function void build_phase(uvm_phase phase);     super.build_phase(phase);     `uvm_info("DRIVER_CLASS", "Build Phase!", UVM_HIGH) //1. driver class template change  :  in the top testbench  module we just set the interface now we need to get the interface so we can get that // interface in  driver class and monitor class // we can get that interface in any function that we want to but ideal way is to get it in the build phase // so let's do it in  the build phase of driver class // The line: uvm_config_db #(virtual SimpleDUT_interface)::get(this, "*", "vif", vif) represents the usage of the uvm_config_db class and its get method in the context of the UVM (Universal Verification Methodology) framework in SystemVerilog.The get method is used to retrieve a configuration setting from the database. // Overall, the line of code retrieves the configuration setting named "vif" of type SimpleDUT_interface from the configuration database, using the current object as the context, and stores the retrieved value in the variable vif // "get"  takes four arguments // first is the class that is requesting: #(virtual SimpleDUT_interface): This is a parameterized type indicating the type of the configuration setting being retrieved. In this case, it is a virtual interface type named SimpleDUT_interface // so first plus second makes the path of the class that is requesting the virtual interface handle and //  then the name that we set for that handle which is"vif": // this: The first argument to the get method represents the context from which the configuration is being retrieved. In this case, it refers to the current object or component where this line of code is executed. // "*": The second argument is a string representing the hierarchical path or scope within the configuration database. In this case, "*" is a wildcard indicating that the configuration can be retrieved from any level of the hierarchy. // "vif": The third argument is a string representing the name of the configuration setting being retrieved. In this case, it is "vif". // vif: The fourth argument is a variable that will receive the retrieved configuration value. In this case, it is a variable named vif of type SimpleDUT_interface. // thing is that we are calling this get method but // what if this fails and it does not get the handle?  If it is not able to get // the interface handle what we should do then?  So let's keep a safety check if(!(uvm_config_db #(virtual SimpleDUT_interface)::get(this, "*", "vif", vif))) begin       `uvm_error("DRIVER_CLASS", "Failed to get VIF from config DB!") end endfunction: build_phase   //--------------------------------------------------------   //Connect Phase   //--------------------------------------------------------   function void connect_phase(uvm_phase phase);     super.connect_phase(phase);     `uvm_info("DRIVER_CLASS", "Connect Phase!", UVM_HIGH)   endfunction: connect_phase   //--------------------------------------------------------   //Run Phase   //--------------------------------------------------------   task run_phase (uvm_phase phase);     super.run_phase(phase);     `uvm_info("DRIVER_CLASS", "Run Phase!", UVM_HIGH) //4. driver class template change  : // what does a driver do? A driver drives the  logic that we want to use to simulate the DUT. // let's just drive the inputs to the interface with this handle (vif) // What we want to do is:  forever run this driver task until the // simulation ends. In other words, forever keep driving these transactions. // And what do we want to drive?  We want to drive this packet which is called “item”. // Logic forever begin     // Create "item"       item = SimpleDUT_sequence_item::type_id::create("item");         // then we use the ports that we declared in the agent (seq_item_port)       // we just use this port inside the driver to get the sequences from the sequencer and to do that we use               // this method:  get_next_item       seq_item_port.get_next_item(item);           // Logic is written here:  A task to drive an "item".     //  We can just create a task that can drive the items although it's not necessary to create create this   // task you can just easily write down here  whatever the logic is.    // On the other hand writing a task is an   // easy way so that in case you need to change something in driver class or   // drive method; this way it does not affect the Run phase, and the Run phase is the most important phase    // in driver class.       drive(item);     //after doing or driving something we can just call seq_item_port.item_done()     //   indicating that we are done driving the item and we are ready to move on to get next item       seq_item_port.item_done();     end     endtask: run_phase //5. driver class template change  : // Here  is task "drive" and it also using the item object that is passed by reference // We want to drive the packet transaction on the interface // but we want to do it only on the positive edge of the clock.  // Where is that clock,  where can we access that clock ?  // We can access that clock from virtual interface handle that we already have // and we use non-blocking assignments although it's not necessary though. //--------------------------------------------------------   //[Method] Drive   //--------------------------------------------------------   task drive(SimpleDUT_sequence_item item);     @(posedge vif.clock);     vif.reset <= item.reset;     vif.din_i <= item.din_i;   endtask: drive endclass: SimpleDUT_driver

Monitor class  template ( one more Component class )

class SimpleDUT_monitor extends uvm_monitor;   `uvm_component_utils(SimpleDUT_monitor)   //--------------------------------------------------------   //Constructor   //--------------------------------------------------------   function new(string name = "SimpleDUT_monitor", uvm_component parent);     super.new(name, parent);     `uvm_info("MONITOR_CLASS", "Inside Constructor!", UVM_HIGH)   endfunction: new   //--------------------------------------------------------   //Build Phase   //--------------------------------------------------------   function void build_phase(uvm_phase phase);     super.build_phase(phase);     `uvm_info("MONITOR_CLASS", "Build Phase!", UVM_HIGH) endfunction: build_phase   //--------------------------------------------------------   //Connect Phase   //--------------------------------------------------------   function void connect_phase(uvm_phase phase);     super.connect_phase(phase);     `uvm_info("MONITOR_CLASS", "Connect Phase!", UVM_HIGH)   endfunction: connect_phase   //--------------------------------------------------------   //Run Phase   //--------------------------------------------------------   task run_phase (uvm_phase phase);     super.run_phase(phase);     `uvm_info("MONITOR_CLASS", "Run Phase!", UVM_HIGH)   // Logic     endtask: run_phase endclass: SimpleDUT_monitor

Monitor class(final solution based of the Monitor class template )

class SimpleDUT_monitor extends uvm_monitor;   `uvm_component_utils(SimpleDUT_monitor) //2. monitor class template change :   // Now when we access that “vif” from the uvm_config_db // also  we want to copy or use a name that we // can use throughout the monitor for that class. // We can use “vif” name  so we do need a handle for this. // We do need to declare it in the class somewhere here so what we // declare is virtual SimpleDUT_interface and the handle would be // “vif”  so that we know that this is virtual interface inside the monitor virtual SimpleDUT_interface vif; //3. monitor class template change :  // In the monitor class we are sampling from the interface // also we will need a name of the handle to the item class that we are going to use in monitor. // we can name this any name uh you want to but let's keep it “item” for simplicity     SimpleDUT_sequence_item item; // 5. monitor class template change : // What scoreboard does (and  what we are doing) is: // from the driver we are driving the transactions one by one on the interface. // The monitor will sample those inputs and then scoreboard will compare // if the result that we expect versus the result that is actual from the DUT // is correct or not. // One thing we need to see is how are we going to connect the scoreboard and // monitor so it is going to be done  just like how we connected the driver and sequencer // Note* a friendly reminder from agent.sv how we connected the driver and sequence: // drv.seq_item_port.connect(seqr.seq_item_export); // driver and sequencer had these ports ( e.g. seq_item_port.connect)  by default but monitor and // scoreboard does not have them so we need to create those ports with uvm_analysis_port. // syntax is something like this:  uvm_analysis_port // and then we pass the parameter we say that what kind of sequence item are we going to drive through these ports. // Basically we say that we are going to drive packet of type SimpleDUT_sequence_item and  // then we can name the port as “monitor_port” // and then we also need to create monitor_port for example in build phase // we need to pass two arguments first is the name of the port and second is the parent uvm_analysis_port #(SimpleDUT_sequence_item) monitor_port;   //--------------------------------------------------------   //Constructor   //--------------------------------------------------------   function new(string name = "SimpleDUT_monitor", uvm_component parent);     super.new(name, parent);     `uvm_info("MONITOR_CLASS", "Inside Constructor!", UVM_HIGH)   endfunction: new   //--------------------------------------------------------   //Build Phase   //--------------------------------------------------------   function void build_phase(uvm_phase phase);     super.build_phase(phase);     `uvm_info("MONITOR_CLASS", "Build Phase!", UVM_HIGH) // 6. monitor class template change : // We need to create monitor_port for example in build phase // we need to pass two arguments first is the name of the port and second is the parent monitor_port = new("monitor_port", this); //1. monitor class template change :  in the top testbench  module we just set the interface now we need to get the interface so we can get that // interface in  driver class and monitor class // we can get that interface in any function that we want to but ideal way is to get it in the build phase // so let's do it in  the build phase of driver class // The line: uvm_config_db #(virtual SimpleDUT_interface)::get(this, "*", "vif", vif) represents the usage of the uvm_config_db class and its get method in the context of the UVM (Universal Verification Methodology) framework in SystemVerilog.The get method is used to retrieve a configuration setting from the database. // Overall, the line of code retrieves the configuration setting named "vif" of type SimpleDUT_interface from the configuration database, using the current object as the context, and stores the retrieved value in the variable vif // "get"  takes four arguments // first is the class that is requesting: #(virtual SimpleDUT_interface): This is a parameterized type indicating the type of the configuration setting being retrieved. In this case, it is a virtual interface type named SimpleDUT_interface // so first plus second makes the path of the class that is requesting the virtual interface handle and //  then the name that we set for that handle which is"vif": // this: The first argument to the get method represents the context from which the configuration is being retrieved. In this case, it refers to the current object or component where this line of code is executed. // "*": The second argument is a string representing the hierarchical path or scope within the configuration database. In this case, "*" is a wildcard indicating that the configuration can be retrieved from any level of the hierarchy. // "vif": The third argument is a string representing the name of the configuration setting being retrieved. In this case, it is "vif". // vif: The fourth argument is a variable that will receive the retrieved configuration value. In this case, it is a variable named vif of type SimpleDUT_interface. // thing is that we are calling this get method but // what if this fails and it does not get the handle?  If it is not able to get // the interface handle what we should do then?  So let's keep a safety check if(!(uvm_config_db #(virtual SimpleDUT_interface)::get(this, "*", "vif", vif))) begin       `uvm_error("MONITOR_CLASS", "Failed to get VIF from config DB!") end endfunction: build_phase   //--------------------------------------------------------   //Connect Phase   //--------------------------------------------------------   function void connect_phase(uvm_phase phase);     super.connect_phase(phase);     `uvm_info("MONITOR_CLASS", "Connect Phase!", UVM_HIGH)   endfunction: connect_phase   //--------------------------------------------------------   //Run Phase   //--------------------------------------------------------   task run_phase (uvm_phase phase);     super.run_phase(phase);     `uvm_info("MONITOR_CLASS", "Run Phase!", UVM_HIGH) //4. monitor class template change : // What we want to do is:  forever run this until the // simulation ends in other words forever keep  monitoring  these transactions. // We want to sample both the input and the output. // Here I am using blocking because it is a general practice to use non-blocking for driver and blocking for // monitor class but if you use otherwise that is also completely fine.   // Logic forever begin       item = SimpleDUT_sequence_item::type_id::create("item");             wait(!vif.reset);             //sample inputs       @(posedge vif.clock);       item.din_i = vif.din_i;       //sample output       // @(posedge vif.clock);       item.dout_o = vif.dout_o;             // 7. monitor class template change:  send item to scoreboard through the port: use method "write"       // to write "item" to scoreboard using port "monitor_port"       //  we also need to implement this "write" method inside the scoreboard       monitor_port.write(item);     end     endtask: run_phase endclass: SimpleDUT_monitor

Sequencer class  template ( once more Component class )

Note #1: Same as driver class, the sequencer class  is a parameterized class so we need to pass the name of the sequence item class that we are going to use 

• we haven't created the sequence item class but I know the name of it will be: SimpleDUT_sequence_item)

• e.g. class SimpleDUT_sequencer extends uvm_sequencer#(SimpleDUT_sequence_item);

Note# 2: also in the sequencer we don't need the “run” phase so I'll just comment out  that part 

• actually we are not going to use any phases in sequencer but just since this is a basic test bench let’s keep it here anyway.

// Note #1: Same as driver class, the sequencer class  is a parameterized class so we need to pass the name of the sequence item class that we are going to use // we haven't created the sequence item class but I know the name of it will be SimpleDUT_sequence_item) // class SimpleDUT_sequencer extends uvm_sequencer;   class SimpleDUT_sequencer extends uvm_sequencer#(SimpleDUT_sequence_item);   `uvm_component_utils(SimpleDUT_sequencer)     //--------------------------------------------------------   //Constructor   //--------------------------------------------------------   function new(string name = "SimpleDUT_sequencer", uvm_component parent);     super.new(name, parent);     `uvm_info("SEQUENCER_CLASS", "Inside Constructor!", UVM_HIGH)   endfunction: new     //--------------------------------------------------------   //Build Phase   //--------------------------------------------------------   function void build_phase(uvm_phase phase);     super.build_phase(phase);     `uvm_info("SEQUENCER_CLASS", "Build Phase!", UVM_HIGH)   endfunction: build_phase     //--------------------------------------------------------   //Connect Phase   //--------------------------------------------------------   function void connect_phase(uvm_phase phase);     super.connect_phase(phase);     `uvm_info("SEQUENCER_CLASS", "Connect Phase!", UVM_HIGH)   endfunction: connect_phase   // Note# 2: also in the sequencer we don't need the Run phase so I'll just comment out  that part   /*   //--------------------------------------------------------   //Run Phase   //--------------------------------------------------------   task run_phase (uvm_phase phase);     super.run_phase(phase);     `uvm_info("SEQUENCER_CLASS", "Run Phase!", UVM_HIGH)   // Logic     endtask: run_phase   */ endclass: SimpleDUT_sequencer

Sequence item class  template ( an OBJECT class)

The sequence item class  is an object class and not a component class so I won't copy

everything from the previous component class  templates.

//Object class class SimpleDUT_sequence_item extends uvm_sequence_item; // just like the component class this class will also need a macro but it will be UVM object utils   `uvm_object_utils(SimpleDUT_sequence_item) // Instantiation logic/wires/registers same as used in interface go here // so in other words: straight copy from interface // We are going to use this to generate random values about DUT input port values on one hand and to store the output result on the other hand. // So to do that what we are going to do is declare these signals as DUT input port values Rand signals   //--------------------------------------------------------   //Instantiation   //--------------------------------------------------------   rand logic [3:0] din_i;   logic [3:0] dout_o; // let's see how Constructor for an object class will be defined:  // In object class Constructor  we just pass the name which can be done  like this   //--------------------------------------------------------   //Constructor   //--------------------------------------------------------   function new(string name = "SimpleDUT_sequence_item");     super.new(name);   endfunction: new endclass: SimpleDUT_sequence_item

Sequence item class(final solution based of the Sequence item class template )

class SimpleDUT_sequence_item extends uvm_sequence_item;   `uvm_object_utils(SimpleDUT_sequence_item)   //--------------------------------------------------------   //Instantiation   //--------------------------------------------------------   rand logic reset ;   rand logic [3:0] din_i;   logic [3:0] dout_o;   // 1. change of SimpleDUT_sequence_item template:  let's put some default constraints that we want in our sequence item   //--------------------------------------------------------   //Default Constraints   //--------------------------------------------------------   constraint input1_c { din_i inside {[0:15]};}     //--------------------------------------------------------   //Constructor   //--------------------------------------------------------   function new(string name = "SimpleDUT_sequence_item");     super.new(name);   endfunction: new endclass: SimpleDUT_sequence_item

Base sequence class template ( an OBJECT class, file: sequence.sv )

class SimpleDUT_base_sequence extends uvm_sequence;   `uvm_object_utils(SimpleDUT_base_sequence)   //--------------------------------------------------------   //Constructor   //--------------------------------------------------------   function new(string name= "SimpleDUT_base_sequence");     super.new(name);     `uvm_info("BASE_SEQ", "Inside Constructor!", UVM_HIGH)   endfunction // in sequence class we need to define // body describing what is going to happen  when we call this sequence   //--------------------------------------------------------   //Body Task   //--------------------------------------------------------   task body();     `uvm_info("BASE_SEQ", "Inside body task!", UVM_HIGH)           endtask: body   endclass: SimpleDUT_base_sequence // we can also create another sequence class SimpleDUT_test_sequence extends SimpleDUT_base_sequence;   `uvm_object_utils(SimpleDUT_test_sequence)     SimpleDUT_sequence_item item;     //--------------------------------------------------------   //Constructor   //--------------------------------------------------------   function new(string name= "SimpleDUT_test_sequence");     super.new(name);     `uvm_info("TEST_SEQ", "Inside Constructor!", UVM_HIGH)   endfunction       //--------------------------------------------------------   //Body Task   //--------------------------------------------------------   task body();     `uvm_info("TEST_SEQ", "Inside body task!", UVM_HIGH)       endtask: body     endclass: SimpleDUT_test_sequence

Base sequence class(final solution based of the Base sequence item class template )

class SimpleDUT_base_sequence extends uvm_sequence;   `uvm_object_utils(SimpleDUT_base_sequence) //1. Change based on Base sequence item class template:    // In a sequence class  we need to start a basic sequence. // This means that the sequence class  will start or generate a sequence item class packets and then send them to the driver. // In order to do that we need to instantiate a sequence item class over here. // let's call it reset_pk SimpleDUT_sequence_item reset_pkt;   //--------------------------------------------------------   //Constructor   //--------------------------------------------------------   function new(string name= "SimpleDUT_base_sequence");     super.new(name);     `uvm_info("BASE_SEQ", "Inside Constructor!", UVM_HIGH)   endfunction   //--------------------------------------------------------   //Body Task   //--------------------------------------------------------   task body();     `uvm_info("BASE_SEQ", "Inside body task!", UVM_HIGH) // 2. Change based on Base sequence item class template: // Further we need to send the reset_pkt to the driver // First step is to create the packet. for this so we say reset_pkt = SimpleDUT_sequence_item …., // and then  we call the “create” method of type_id create. // Finally we say that a name of our packet is "reset_pkt"( you can give any name here) // 3. Change based on Base sequence item class template:  // Next we need to start_item and finish_item. // Here we want to randomize that package although with “reset” constraint to be only one value: 1. // As a result this sequence will just reset the DUT ( assumption here is that “reset” is active high.     reset_pkt = SimpleDUT_sequence_item::type_id::create("reset_pkt");     start_item(reset_pkt);   // Since constraint on the “reset” tigh reset to 1   // this sequence will just reset the duty that we have ( the reset is active high )       reset_pkt.randomize() with {reset==1;};     finish_item(reset_pkt);           endtask: body   endclass: SimpleDUT_base_sequence

// 4. Change based on Base sequence item class template: //  we can also create another sequence which is not reset sequence class SimpleDUT_test_sequence extends SimpleDUT_base_sequence;   `uvm_object_utils(SimpleDUT_test_sequence)     SimpleDUT_sequence_item item;     //--------------------------------------------------------   //Constructor   //--------------------------------------------------------   function new(string name= "SimpleDUT_test_sequence");     super.new(name);     `uvm_info("TEST_SEQ", "Inside Constructor!", UVM_HIGH)   endfunction       //--------------------------------------------------------   //Body Task   //--------------------------------------------------------   task body();     `uvm_info("TEST_SEQ", "Inside body task!", UVM_HIGH) // 5. Change based on Base sequence item class template:   // In this test sequence the randomized “reset” is equal to zero because now with this sequence we don't want uh to reset anything. This time  we want to drive some values to the input of DUT. item = SimpleDUT_sequence_item::type_id::create("item");     start_item(item);       item.randomize() with {reset==0;};     finish_item(item);       endtask: body     endclass: SimpleDUT_test_sequence

now let's code the scoreboard ( component class)

Let’s start with UVM scoreboard component class template code and then keep expanding the code also  including numerated new code comments.

class SimpleDUT_scoreboard extends uvm_test;   `uvm_component_utils(SimpleDUT_scoreboard) //1. Change to UVM scoreboard component class template // Similar to the monitor class,  we need to do something similar for the scoreboard port. // Now the caveat is that driver will be sending packets, so in drivers case the port will be a transmitter port (uses uvm_analysis_port) // Scoreboard will need a receiver port so Scoreboard port will be a receiver port ( uses: uvm_analysis_imp ). // uvm_analysis_imp has two parameters:  one is the sequence item, and here  we are going to use // SimpleDUT_sequence_item and the other is the name of the scoreboard (SimpleDUT_scoreboard). // Finally we can call this port as  scoreboard_port. uvm_analysis_imp #(SimpleDUT_sequence_item, SimpleDUT_scoreboard) scoreboard_port; //4. Change to UVM scoreboard component class template   //  let's say monitor sends or writes   // this item in the port and scoreboard will receive it so what we need to do is   // make a database or store that item or packets let's say  we want to run   // the sequence 100 times and we want to save all those 100 transactions so we   // can use a data structure to save all the packets. Easiest data structure   // is the queue that we can use here so that it becomes a sort of a fifo.   // As a conclusion here we are going to  create a queue  of type   // sequence item and we can call this queue:  transactions. SimpleDUT_sequence_item transactions[$];   //--------------------------------------------------------   //Constructor   //--------------------------------------------------------   function new(string name = "SimpleDUT_scoreboard", uvm_component parent);     super.new(name, parent);     `uvm_info("SCB_CLASS", "Inside Constructor!", UVM_HIGH)   endfunction: new     //--------------------------------------------------------   //Build Phase   //--------------------------------------------------------   function void build_phase(uvm_phase phase);     super.build_phase(phase);     `uvm_info("SCB_CLASS", "Build Phase!", UVM_HIGH)     //2. Change to UVM scoreboard component class template     //   scoreboard_port we need to construct/create in for example build phase     scoreboard_port = new("scoreboard_port", this);   endfunction: build_phase     //--------------------------------------------------------   //Connect Phase   //--------------------------------------------------------   function void connect_phase(uvm_phase phase);     super.connect_phase(phase);     `uvm_info("SCB_CLASS", "Connect Phase!", UVM_HIGH)   endfunction: connect_phase     // 3. Change to UVM scoreboard component class template    // We also need to implement the "write" method ( from monitor class line: monitor_port.write(item);):   // this is the most important part of the scoreboard:  write method.   // The write method determines what is going to happen when monitor sends the item in the   // scoreboard.   // We are implementing this method here and that's why the name over   // here is:  uvm_analysis_imp #((SimpleDUT_sequence_item, SimpleDUT_scoreboard) scoreboard_port; uvm_analysis_imp stands for implementation).      // The port name is UVM analysis implementation (uvm_analysis_imp) because we are   // implementing this write method in this class.   // We also need to pass "item"  as a parameter.   //--------------------------------------------------------   //Write Method   //--------------------------------------------------------   function void write(SimpleDUT_sequence_item item); // Make a database or store that item or packets. // use this transactions.push_back what do we want to push is this item so // one by one whenever this method is called. We are just pushing this item into "transactions" // data structure     transactions.push_back(item); // in the Run phase we will do something about those transactions maybe compare or // something like that   endfunction: write //--------------------------------------------------------   //Run Phase   //--------------------------------------------------------   task run_phase (uvm_phase phase);     super.run_phase(phase);     `uvm_info("SCB_CLASS", "Run Phase!", UVM_HIGH)       //5. Change to UVM scoreboard component class template       // In the Run phase like in other run phases we just want to keep on  running this forever until the     // simulation ends forever begin       /*       // get the packet       // generate expected value       // compare it with actual value       // score the transactions accordingly       */       SimpleDUT_sequence_item curr_trans; // we need to wait for until the transaction queue size becomes greater than 0 // we don't want to run this task of popping up the data from fifo if we have not received any transactions yet.       wait((transactions.size() != 0)); // copy/ pop it from the fifo "transactions" only one transaction at a time and then we play with that in the // forever loop       curr_trans = transactions.pop_front(); //"compare" is task that take as argument that one piece of data we just popped from the fifo       compare(curr_trans);           end     endtask: run_phase //6. Change to UVM scoreboard component class template // Adding compare task:   //--------------------------------------------------------   //Compare : Generate Expected Result and Compare with Actual   //--------------------------------------------------------   task compare(SimpleDUT_sequence_item curr_trans);     logic [3:0] expected;     logic [3:0] actual;     expected = curr_trans.din_i;   actual   = curr_trans.dout_o;         if(actual != expected) begin       `uvm_error("COMPARE", $sformatf("Transaction failed! ACT=%d, EXP=%d", actual, expected))     end     else begin       uvm_info("COMPARE", $sformatf("Transaction Passed! ACT=%d, EXP=%d", actual, expected), UVM_LOW)     end       endtask: compare endclass: SimpleDUT_scoreboard

Verification waveforms

Simulation/Verification log

[2023-07-04 13:46:10 UTC] vcs -licqueue '-timescale=1ns/1ns' '+vcs+flush+all' '+warn=all' '-sverilog' +incdir+$UVM_HOME/src $UVM_HOME/src/uvm.sv $UVM_HOME/src/dpi/uvm_dpi.cc -CFLAGS -DVCS design.sv testbench.sv  && ./simv +vcs+lic+wait '+UVM_VERBOSITY=UVM_HIGH' 

Parsing design file 'design.sv'

Parsing design file 'testbench.sv'

Note-[SV-LCM-PPWI] Package previously wildcard imported

testbench.sv, 5

$unit

 Package 'uvm_pkg' already wildcard imported.

 Ignoring uvm_pkg::*

 See the SystemVerilog LRM(1800-2005), section 19.2.1.

Parsing included file '/apps/vcsmx/vcs/S-2021.09//etc/uvm-1.2/src/uvm_macros.svh'.

Back to file 'testbench.sv'.

Parsing included file 'interface.sv'.

Back to file 'testbench.sv'.

Parsing included file 'sequence_item.sv'.

Back to file 'testbench.sv'.

Parsing included file 'sequence.sv'.

Back to file 'testbench.sv'.

Parsing included file 'sequencer.sv'.

Back to file 'testbench.sv'.

Parsing included file 'driver.sv'.

Back to file 'testbench.sv'.

Parsing included file 'monitor.sv'.

Back to file 'testbench.sv'.

Parsing included file 'agent.sv'.

Back to file 'testbench.sv'.

Parsing included file 'scoreboard.sv'.

Back to file 'testbench.sv'.

Parsing included file 'env.sv'.

Back to file 'testbench.sv'.

Parsing included file 'test.sv'.

Back to file 'testbench.sv'.

Top Level Modules:

      top

TimeScale is 1 ns / 1 ns

Starting vcs inline pass...

6 modules and 0 UDP read.

recompiling package vcs_paramclassrepository

recompiling package _vcs_DPI_package

recompiling package uvm_pkg

recompiling module SimpleDUT

recompiling module SimpleDUT_interface

recompiling module top

All of 6 modules done

rm -f _cuarc*.so _csrc*.so pre_vcsobj_*.so share_vcsobj_*.so

g++ -w  -pipe -m32 -DVCS -O -I/apps/vcsmx/vcs/S-2021.09/include    -c /apps/vcsmx/vcs/S-2021.09//etc/uvm-1.2/src/dpi/uvm_dpi.cc

gcc  -w  -pipe -m32 -DVCS -O -I/apps/vcsmx/vcs/S-2021.09/include     -c -o uM9F1_0x2aB.o uM9F1_0x2aB.c

if [ -x ../simv ]; then chmod a-x ../simv; fi

g++  -o ../simv      -m32 -m32 -rdynamic  -Wl,-rpath='$ORIGIN'/simv.daidir -Wl,-rpath=./simv.daidir -Wl,-rpath=/apps/vcsmx/vcs/S-2021.09/linux/lib -L/apps/vcsmx/vcs/S-2021.09/linux/lib  -Wl,-rpath-link=./ -Wl,--no-as-needed  uvm_dpi.o   objs/amcQw_d.o   _415_archive_1.so  SIM_l.o    uM9F1_0x2aB.o   rmapats_mop.o rmapats.o rmar.o rmar_nd.o  rmar_llvm_0_1.o rmar_llvm_0_0.o           -lvirsim -lerrorinf -lsnpsmalloc -lvfs    -lvcsnew -lsimprofile -luclinative /apps/vcsmx/vcs/S-2021.09/linux/lib/vcs_tls.o   -Wl,-whole-archive  -lvcsucli    -Wl,-no-whole-archive       ./../simv.daidir/vc_hdrs.o    /apps/vcsmx/vcs/S-2021.09/linux/lib/vcs_save_restore_new.o /apps/vcsmx/vcs/S-2021.09/linux/lib/ctype-stubs_32.a -ldl  -lc -lm -lpthread -ldl

../simv up to date

CPU time: 11.771 seconds to compile + .498 seconds to elab + .645 seconds to link

Chronologic VCS simulator copyright 1991-2021

Contains Synopsys proprietary information.

Compiler version S-2021.09; Runtime version S-2021.09;  Jul  4 09:46 2023

UVM_INFO /apps/vcsmx/vcs/S-2021.09//etc/uvm-1.2/src/base/uvm_root.svh(402) @ 0: reporter [UVM/RELNOTES]

----------------------------------------------------------------

UVM-1.2.Synopsys

(C) 2007-2014 Mentor Graphics Corporation

(C) 2007-2014 Cadence Design Systems, Inc.

(C) 2006-2014 Synopsys, Inc.

(C) 2011-2013 Cypress Semiconductor Corp.

(C) 2013-2014 NVIDIA Corporation

----------------------------------------------------------------

 

UVM_INFO test.sv(31) @ 0: uvm_test_top [TEST_CLASS] Inside Constructor!

UVM_INFO @ 0: reporter [RNTST] Running test SimpleDUT_test...

UVM_INFO test.sv(39) @ 0: uvm_test_top [TEST_CLASS] Build Phase!

UVM_INFO env.sv(30) @ 0: uvm_test_top.env [ENV_CLASS] Inside Constructor!

UVM_INFO env.sv(39) @ 0: uvm_test_top.env [ENV_CLASS] Build Phase!

UVM_INFO agent.sv(18) @ 0: uvm_test_top.env.agnt [AGENT_CLASS] Inside Constructor!

UVM_INFO scoreboard.sv(30) @ 0: uvm_test_top.env.scb [SCB_CLASS] Inside Constructor!

UVM_INFO agent.sv(28) @ 0: uvm_test_top.env.agnt [AGENT_CLASS] Build Phase!

UVM_INFO driver.sv(28) @ 0: uvm_test_top.env.agnt.drv [DRIVER_CLASS] Inside Constructor!

UVM_INFO monitor.sv(47) @ 0: uvm_test_top.env.agnt.mon [MONITOR_CLASS] Inside Constructor!

UVM_INFO sequencer.sv(14) @ 0: uvm_test_top.env.agnt.seqr [SEQUENCER_CLASS] Inside Constructor!

UVM_INFO driver.sv(38) @ 0: uvm_test_top.env.agnt.drv [DRIVER_CLASS] Build Phase!

UVM_INFO monitor.sv(57) @ 0: uvm_test_top.env.agnt.mon [MONITOR_CLASS] Build Phase!

UVM_INFO sequencer.sv(24) @ 0: uvm_test_top.env.agnt.seqr [SEQUENCER_CLASS] Build Phase!

UVM_INFO scoreboard.sv(40) @ 0: uvm_test_top.env.scb [SCB_CLASS] Build Phase!

UVM_INFO driver.sv(72) @ 0: uvm_test_top.env.agnt.drv [DRIVER_CLASS] Connect Phase!

UVM_INFO monitor.sv(96) @ 0: uvm_test_top.env.agnt.mon [MONITOR_CLASS] Connect Phase!

UVM_INFO sequencer.sv(34) @ 0: uvm_test_top.env.agnt.seqr [SEQUENCER_CLASS] Connect Phase!

UVM_INFO agent.sv(43) @ 0: uvm_test_top.env.agnt [AGENT_CLASS] Connect Phase!

UVM_INFO scoreboard.sv(53) @ 0: uvm_test_top.env.scb [SCB_CLASS] Connect Phase!

UVM_INFO env.sv(66) @ 0: uvm_test_top.env [ENV_CLASS] Connect Phase!

UVM_INFO test.sv(64) @ 0: uvm_test_top [TEST_CLASS] Connect Phase!

UVM_INFO driver.sv(83) @ 0: uvm_test_top.env.agnt.drv [DRIVER_CLASS] Run Phase!

UVM_INFO monitor.sv(106) @ 0: uvm_test_top.env.agnt.mon [MONITOR_CLASS] Run Phase!

UVM_INFO agent.sv(62) @ 0: uvm_test_top.env.agnt [AGENT_CLASS] Run Phase!

UVM_INFO scoreboard.sv(94) @ 0: uvm_test_top.env.scb [SCB_CLASS] Run Phase!

UVM_INFO env.sv(86) @ 0: uvm_test_top.env [ENV_CLASS] Run Phase!

UVM_INFO test.sv(72) @ 0: uvm_test_top [TEST_CLASS] Run Phase!

UVM_INFO sequence.sv(17) @ 0: reporter@@reset_seq [BASE_SEQ] Inside Constructor!

UVM_INFO sequence.sv(23) @ 0: uvm_test_top.env.agnt.seqr@@reset_seq [BASE_SEQ] Inside body task!

UVM_INFO sequence.sv(17) @ 15: reporter@@test_seq [BASE_SEQ] Inside Constructor!

UVM_INFO sequence.sv(61) @ 15: reporter@@test_seq [TEST_SEQ] Inside Constructor!

UVM_INFO sequence.sv(69) @ 15: uvm_test_top.env.agnt.seqr@@test_seq [TEST_SEQ] Inside body task!

UVM_INFO scoreboard.sv(145) @ 21: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT= 6, EXP= 6

UVM_INFO scoreboard.sv(145) @ 25: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT= 6, EXP= 6

UVM_INFO sequence.sv(17) @ 27: reporter@@test_seq [BASE_SEQ] Inside Constructor!

UVM_INFO sequence.sv(61) @ 27: reporter@@test_seq [TEST_SEQ] Inside Constructor!

UVM_INFO sequence.sv(69) @ 27: uvm_test_top.env.agnt.seqr@@test_seq [TEST_SEQ] Inside body task!

UVM_INFO scoreboard.sv(145) @ 29: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT= 6, EXP= 6

UVM_INFO scoreboard.sv(145) @ 33: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT=11, EXP=11

UVM_INFO scoreboard.sv(145) @ 37: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT=11, EXP=11

UVM_INFO sequence.sv(17) @ 39: reporter@@test_seq [BASE_SEQ] Inside Constructor!

UVM_INFO sequence.sv(61) @ 39: reporter@@test_seq [TEST_SEQ] Inside Constructor!

UVM_INFO sequence.sv(69) @ 39: uvm_test_top.env.agnt.seqr@@test_seq [TEST_SEQ] Inside body task!

UVM_INFO scoreboard.sv(145) @ 41: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT=11, EXP=11

UVM_INFO scoreboard.sv(145) @ 45: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT=12, EXP=12

UVM_INFO scoreboard.sv(145) @ 49: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT=12, EXP=12

UVM_INFO sequence.sv(17) @ 51: reporter@@test_seq [BASE_SEQ] Inside Constructor!

UVM_INFO sequence.sv(61) @ 51: reporter@@test_seq [TEST_SEQ] Inside Constructor!

UVM_INFO sequence.sv(69) @ 51: uvm_test_top.env.agnt.seqr@@test_seq [TEST_SEQ] Inside body task!

UVM_INFO scoreboard.sv(145) @ 53: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT=12, EXP=12

UVM_INFO scoreboard.sv(145) @ 57: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT= 7, EXP= 7

UVM_INFO scoreboard.sv(145) @ 61: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT= 7, EXP= 7

UVM_INFO sequence.sv(17) @ 63: reporter@@test_seq [BASE_SEQ] Inside Constructor!

UVM_INFO sequence.sv(61) @ 63: reporter@@test_seq [TEST_SEQ] Inside Constructor!

UVM_INFO sequence.sv(69) @ 63: uvm_test_top.env.agnt.seqr@@test_seq [TEST_SEQ] Inside body task!

UVM_INFO scoreboard.sv(145) @ 65: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT= 7, EXP= 7

UVM_INFO scoreboard.sv(145) @ 69: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT=13, EXP=13

UVM_INFO scoreboard.sv(145) @ 73: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT=13, EXP=13

UVM_INFO sequence.sv(17) @ 75: reporter@@test_seq [BASE_SEQ] Inside Constructor!

UVM_INFO sequence.sv(61) @ 75: reporter@@test_seq [TEST_SEQ] Inside Constructor!

UVM_INFO sequence.sv(69) @ 75: uvm_test_top.env.agnt.seqr@@test_seq [TEST_SEQ] Inside body task!

UVM_INFO scoreboard.sv(145) @ 77: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT=13, EXP=13

UVM_INFO scoreboard.sv(145) @ 81: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT=14, EXP=14

UVM_INFO scoreboard.sv(145) @ 85: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT=14, EXP=14

UVM_INFO sequence.sv(17) @ 87: reporter@@test_seq [BASE_SEQ] Inside Constructor!

UVM_INFO sequence.sv(61) @ 87: reporter@@test_seq [TEST_SEQ] Inside Constructor!

UVM_INFO sequence.sv(69) @ 87: uvm_test_top.env.agnt.seqr@@test_seq [TEST_SEQ] Inside body task!

UVM_INFO scoreboard.sv(145) @ 89: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT=14, EXP=14

UVM_INFO scoreboard.sv(145) @ 93: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT= 4, EXP= 4

UVM_INFO scoreboard.sv(145) @ 97: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT= 4, EXP= 4

UVM_INFO sequence.sv(17) @ 99: reporter@@test_seq [BASE_SEQ] Inside Constructor!

UVM_INFO sequence.sv(61) @ 99: reporter@@test_seq [TEST_SEQ] Inside Constructor!

UVM_INFO sequence.sv(69) @ 99: uvm_test_top.env.agnt.seqr@@test_seq [TEST_SEQ] Inside body task!

UVM_INFO scoreboard.sv(145) @ 101: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT= 4, EXP= 4

UVM_INFO scoreboard.sv(145) @ 105: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT=11, EXP=11

UVM_INFO scoreboard.sv(145) @ 109: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT=11, EXP=11

UVM_INFO sequence.sv(17) @ 111: reporter@@test_seq [BASE_SEQ] Inside Constructor!

UVM_INFO sequence.sv(61) @ 111: reporter@@test_seq [TEST_SEQ] Inside Constructor!

UVM_INFO sequence.sv(69) @ 111: uvm_test_top.env.agnt.seqr@@test_seq [TEST_SEQ] Inside body task!

UVM_INFO scoreboard.sv(145) @ 113: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT=11, EXP=11

UVM_INFO scoreboard.sv(145) @ 117: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT= 4, EXP= 4

UVM_INFO scoreboard.sv(145) @ 121: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT= 4, EXP= 4

UVM_INFO sequence.sv(17) @ 123: reporter@@test_seq [BASE_SEQ] Inside Constructor!

UVM_INFO sequence.sv(61) @ 123: reporter@@test_seq [TEST_SEQ] Inside Constructor!

UVM_INFO sequence.sv(69) @ 123: uvm_test_top.env.agnt.seqr@@test_seq [TEST_SEQ] Inside body task!

UVM_INFO scoreboard.sv(145) @ 125: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT= 4, EXP= 4

UVM_INFO scoreboard.sv(145) @ 129: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT=15, EXP=15

UVM_INFO scoreboard.sv(145) @ 133: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT=15, EXP=15

UVM_INFO sequence.sv(17) @ 135: reporter@@test_seq [BASE_SEQ] Inside Constructor!

UVM_INFO sequence.sv(61) @ 135: reporter@@test_seq [TEST_SEQ] Inside Constructor!

UVM_INFO sequence.sv(69) @ 135: uvm_test_top.env.agnt.seqr@@test_seq [TEST_SEQ] Inside body task!

UVM_INFO scoreboard.sv(145) @ 137: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT=15, EXP=15

UVM_INFO scoreboard.sv(145) @ 141: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT=11, EXP=11

UVM_INFO scoreboard.sv(145) @ 145: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT=11, EXP=11

UVM_INFO sequence.sv(17) @ 147: reporter@@test_seq [BASE_SEQ] Inside Constructor!

UVM_INFO sequence.sv(61) @ 147: reporter@@test_seq [TEST_SEQ] Inside Constructor!

UVM_INFO sequence.sv(69) @ 147: uvm_test_top.env.agnt.seqr@@test_seq [TEST_SEQ] Inside body task!

UVM_INFO scoreboard.sv(145) @ 149: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT=11, EXP=11

UVM_INFO scoreboard.sv(145) @ 153: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT= 2, EXP= 2

UVM_INFO scoreboard.sv(145) @ 157: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT= 2, EXP= 2

UVM_INFO sequence.sv(17) @ 159: reporter@@test_seq [BASE_SEQ] Inside Constructor!

UVM_INFO sequence.sv(61) @ 159: reporter@@test_seq [TEST_SEQ] Inside Constructor!

UVM_INFO sequence.sv(69) @ 159: uvm_test_top.env.agnt.seqr@@test_seq [TEST_SEQ] Inside body task!

UVM_INFO scoreboard.sv(145) @ 161: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT= 2, EXP= 2

UVM_INFO scoreboard.sv(145) @ 165: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT= 7, EXP= 7

UVM_INFO scoreboard.sv(145) @ 169: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT= 7, EXP= 7

UVM_INFO sequence.sv(17) @ 171: reporter@@test_seq [BASE_SEQ] Inside Constructor!

UVM_INFO sequence.sv(61) @ 171: reporter@@test_seq [TEST_SEQ] Inside Constructor!

UVM_INFO sequence.sv(69) @ 171: uvm_test_top.env.agnt.seqr@@test_seq [TEST_SEQ] Inside body task!

UVM_INFO scoreboard.sv(145) @ 173: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT= 7, EXP= 7

UVM_INFO scoreboard.sv(145) @ 177: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT=10, EXP=10

UVM_INFO scoreboard.sv(145) @ 181: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT=10, EXP=10

UVM_INFO sequence.sv(17) @ 183: reporter@@test_seq [BASE_SEQ] Inside Constructor!

UVM_INFO sequence.sv(61) @ 183: reporter@@test_seq [TEST_SEQ] Inside Constructor!

UVM_INFO sequence.sv(69) @ 183: uvm_test_top.env.agnt.seqr@@test_seq [TEST_SEQ] Inside body task!

UVM_INFO scoreboard.sv(145) @ 185: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT=10, EXP=10

UVM_INFO scoreboard.sv(145) @ 189: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT= 4, EXP= 4

UVM_INFO scoreboard.sv(145) @ 193: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT= 4, EXP= 4

UVM_INFO sequence.sv(17) @ 195: reporter@@test_seq [BASE_SEQ] Inside Constructor!

UVM_INFO sequence.sv(61) @ 195: reporter@@test_seq [TEST_SEQ] Inside Constructor!

UVM_INFO sequence.sv(69) @ 195: uvm_test_top.env.agnt.seqr@@test_seq [TEST_SEQ] Inside body task!

UVM_INFO scoreboard.sv(145) @ 197: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT= 4, EXP= 4

UVM_INFO scoreboard.sv(145) @ 201: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT= 5, EXP= 5

UVM_INFO scoreboard.sv(145) @ 205: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT= 5, EXP= 5

UVM_INFO sequence.sv(17) @ 207: reporter@@test_seq [BASE_SEQ] Inside Constructor!

UVM_INFO sequence.sv(61) @ 207: reporter@@test_seq [TEST_SEQ] Inside Constructor!

UVM_INFO sequence.sv(69) @ 207: uvm_test_top.env.agnt.seqr@@test_seq [TEST_SEQ] Inside body task!

UVM_INFO scoreboard.sv(145) @ 209: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT= 5, EXP= 5

UVM_INFO scoreboard.sv(145) @ 213: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT= 9, EXP= 9

UVM_INFO scoreboard.sv(145) @ 217: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT= 9, EXP= 9

UVM_INFO sequence.sv(17) @ 219: reporter@@test_seq [BASE_SEQ] Inside Constructor!

UVM_INFO sequence.sv(61) @ 219: reporter@@test_seq [TEST_SEQ] Inside Constructor!

UVM_INFO sequence.sv(69) @ 219: uvm_test_top.env.agnt.seqr@@test_seq [TEST_SEQ] Inside body task!

UVM_INFO scoreboard.sv(145) @ 221: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT= 9, EXP= 9

UVM_INFO scoreboard.sv(145) @ 225: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT=11, EXP=11

UVM_INFO scoreboard.sv(145) @ 229: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT=11, EXP=11

UVM_INFO sequence.sv(17) @ 231: reporter@@test_seq [BASE_SEQ] Inside Constructor!

UVM_INFO sequence.sv(61) @ 231: reporter@@test_seq [TEST_SEQ] Inside Constructor!

UVM_INFO sequence.sv(69) @ 231: uvm_test_top.env.agnt.seqr@@test_seq [TEST_SEQ] Inside body task!

UVM_INFO scoreboard.sv(145) @ 233: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT=11, EXP=11

UVM_INFO scoreboard.sv(145) @ 237: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT= 8, EXP= 8

UVM_INFO scoreboard.sv(145) @ 241: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT= 8, EXP= 8

UVM_INFO sequence.sv(17) @ 243: reporter@@test_seq [BASE_SEQ] Inside Constructor!

UVM_INFO sequence.sv(61) @ 243: reporter@@test_seq [TEST_SEQ] Inside Constructor!

UVM_INFO sequence.sv(69) @ 243: uvm_test_top.env.agnt.seqr@@test_seq [TEST_SEQ] Inside body task!

UVM_INFO scoreboard.sv(145) @ 245: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT= 8, EXP= 8

UVM_INFO scoreboard.sv(145) @ 249: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT= 9, EXP= 9

UVM_INFO scoreboard.sv(145) @ 253: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT= 9, EXP= 9

UVM_INFO sequence.sv(17) @ 255: reporter@@test_seq [BASE_SEQ] Inside Constructor!

UVM_INFO sequence.sv(61) @ 255: reporter@@test_seq [TEST_SEQ] Inside Constructor!

UVM_INFO sequence.sv(69) @ 255: uvm_test_top.env.agnt.seqr@@test_seq [TEST_SEQ] Inside body task!

UVM_INFO scoreboard.sv(145) @ 257: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT= 9, EXP= 9

UVM_INFO scoreboard.sv(145) @ 261: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT=14, EXP=14

UVM_INFO scoreboard.sv(145) @ 265: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT=14, EXP=14

UVM_INFO sequence.sv(17) @ 267: reporter@@test_seq [BASE_SEQ] Inside Constructor!

UVM_INFO sequence.sv(61) @ 267: reporter@@test_seq [TEST_SEQ] Inside Constructor!

UVM_INFO sequence.sv(69) @ 267: uvm_test_top.env.agnt.seqr@@test_seq [TEST_SEQ] Inside body task!

UVM_INFO scoreboard.sv(145) @ 269: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT=14, EXP=14

UVM_INFO scoreboard.sv(145) @ 273: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT=12, EXP=12

UVM_INFO scoreboard.sv(145) @ 277: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT=12, EXP=12

UVM_INFO sequence.sv(17) @ 279: reporter@@test_seq [BASE_SEQ] Inside Constructor!

UVM_INFO sequence.sv(61) @ 279: reporter@@test_seq [TEST_SEQ] Inside Constructor!

UVM_INFO sequence.sv(69) @ 279: uvm_test_top.env.agnt.seqr@@test_seq [TEST_SEQ] Inside body task!

UVM_INFO scoreboard.sv(145) @ 281: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT=12, EXP=12

UVM_INFO scoreboard.sv(145) @ 285: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT= 3, EXP= 3

UVM_INFO scoreboard.sv(145) @ 289: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT= 3, EXP= 3

UVM_INFO sequence.sv(17) @ 291: reporter@@test_seq [BASE_SEQ] Inside Constructor!

UVM_INFO sequence.sv(61) @ 291: reporter@@test_seq [TEST_SEQ] Inside Constructor!

UVM_INFO sequence.sv(69) @ 291: uvm_test_top.env.agnt.seqr@@test_seq [TEST_SEQ] Inside body task!

UVM_INFO scoreboard.sv(145) @ 293: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT= 3, EXP= 3

UVM_INFO scoreboard.sv(145) @ 297: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT= 3, EXP= 3

UVM_INFO scoreboard.sv(145) @ 301: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT= 3, EXP= 3

UVM_INFO sequence.sv(17) @ 303: reporter@@test_seq [BASE_SEQ] Inside Constructor!

UVM_INFO sequence.sv(61) @ 303: reporter@@test_seq [TEST_SEQ] Inside Constructor!

UVM_INFO sequence.sv(69) @ 303: uvm_test_top.env.agnt.seqr@@test_seq [TEST_SEQ] Inside body task!

UVM_INFO scoreboard.sv(145) @ 305: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT= 3, EXP= 3

UVM_INFO scoreboard.sv(145) @ 309: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT= 9, EXP= 9

UVM_INFO scoreboard.sv(145) @ 313: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT= 9, EXP= 9

UVM_INFO sequence.sv(17) @ 315: reporter@@test_seq [BASE_SEQ] Inside Constructor!

UVM_INFO sequence.sv(61) @ 315: reporter@@test_seq [TEST_SEQ] Inside Constructor!

UVM_INFO sequence.sv(69) @ 315: uvm_test_top.env.agnt.seqr@@test_seq [TEST_SEQ] Inside body task!

UVM_INFO scoreboard.sv(145) @ 317: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT= 9, EXP= 9

UVM_INFO scoreboard.sv(145) @ 321: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT= 5, EXP= 5

UVM_INFO scoreboard.sv(145) @ 325: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT= 5, EXP= 5

UVM_INFO sequence.sv(17) @ 327: reporter@@test_seq [BASE_SEQ] Inside Constructor!

UVM_INFO sequence.sv(61) @ 327: reporter@@test_seq [TEST_SEQ] Inside Constructor!

UVM_INFO sequence.sv(69) @ 327: uvm_test_top.env.agnt.seqr@@test_seq [TEST_SEQ] Inside body task!

UVM_INFO scoreboard.sv(145) @ 329: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT= 5, EXP= 5

UVM_INFO scoreboard.sv(145) @ 333: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT= 1, EXP= 1

UVM_INFO scoreboard.sv(145) @ 337: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT= 1, EXP= 1

UVM_INFO sequence.sv(17) @ 339: reporter@@test_seq [BASE_SEQ] Inside Constructor!

UVM_INFO sequence.sv(61) @ 339: reporter@@test_seq [TEST_SEQ] Inside Constructor!

UVM_INFO sequence.sv(69) @ 339: uvm_test_top.env.agnt.seqr@@test_seq [TEST_SEQ] Inside body task!

UVM_INFO scoreboard.sv(145) @ 341: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT= 1, EXP= 1

UVM_INFO scoreboard.sv(145) @ 345: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT= 0, EXP= 0

UVM_INFO scoreboard.sv(145) @ 349: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT= 0, EXP= 0

UVM_INFO sequence.sv(17) @ 351: reporter@@test_seq [BASE_SEQ] Inside Constructor!

UVM_INFO sequence.sv(61) @ 351: reporter@@test_seq [TEST_SEQ] Inside Constructor!

UVM_INFO sequence.sv(69) @ 351: uvm_test_top.env.agnt.seqr@@test_seq [TEST_SEQ] Inside body task!

UVM_INFO scoreboard.sv(145) @ 353: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT= 0, EXP= 0

UVM_INFO scoreboard.sv(145) @ 357: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT= 8, EXP= 8

UVM_INFO scoreboard.sv(145) @ 361: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT= 8, EXP= 8

UVM_INFO sequence.sv(17) @ 363: reporter@@test_seq [BASE_SEQ] Inside Constructor!

UVM_INFO sequence.sv(61) @ 363: reporter@@test_seq [TEST_SEQ] Inside Constructor!

UVM_INFO sequence.sv(69) @ 363: uvm_test_top.env.agnt.seqr@@test_seq [TEST_SEQ] Inside body task!

UVM_INFO scoreboard.sv(145) @ 365: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT= 8, EXP= 8

UVM_INFO scoreboard.sv(145) @ 369: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT= 1, EXP= 1

UVM_INFO scoreboard.sv(145) @ 373: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT= 1, EXP= 1

UVM_INFO sequence.sv(17) @ 375: reporter@@test_seq [BASE_SEQ] Inside Constructor!

UVM_INFO sequence.sv(61) @ 375: reporter@@test_seq [TEST_SEQ] Inside Constructor!

UVM_INFO sequence.sv(69) @ 375: uvm_test_top.env.agnt.seqr@@test_seq [TEST_SEQ] Inside body task!

UVM_INFO scoreboard.sv(145) @ 377: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT= 1, EXP= 1

UVM_INFO scoreboard.sv(145) @ 381: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT=11, EXP=11

UVM_INFO scoreboard.sv(145) @ 385: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT=11, EXP=11

UVM_INFO sequence.sv(17) @ 387: reporter@@test_seq [BASE_SEQ] Inside Constructor!

UVM_INFO sequence.sv(61) @ 387: reporter@@test_seq [TEST_SEQ] Inside Constructor!

UVM_INFO sequence.sv(69) @ 387: uvm_test_top.env.agnt.seqr@@test_seq [TEST_SEQ] Inside body task!

UVM_INFO scoreboard.sv(145) @ 389: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT=11, EXP=11

UVM_INFO scoreboard.sv(145) @ 393: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT= 3, EXP= 3

UVM_INFO scoreboard.sv(145) @ 397: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT= 3, EXP= 3

UVM_INFO sequence.sv(17) @ 399: reporter@@test_seq [BASE_SEQ] Inside Constructor!

UVM_INFO sequence.sv(61) @ 399: reporter@@test_seq [TEST_SEQ] Inside Constructor!

UVM_INFO sequence.sv(69) @ 399: uvm_test_top.env.agnt.seqr@@test_seq [TEST_SEQ] Inside body task!

UVM_INFO scoreboard.sv(145) @ 401: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT= 3, EXP= 3

UVM_INFO scoreboard.sv(145) @ 405: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT=10, EXP=10

UVM_INFO scoreboard.sv(145) @ 409: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT=10, EXP=10

UVM_INFO sequence.sv(17) @ 411: reporter@@test_seq [BASE_SEQ] Inside Constructor!

UVM_INFO sequence.sv(61) @ 411: reporter@@test_seq [TEST_SEQ] Inside Constructor!

UVM_INFO sequence.sv(69) @ 411: uvm_test_top.env.agnt.seqr@@test_seq [TEST_SEQ] Inside body task!

UVM_INFO scoreboard.sv(145) @ 413: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT=10, EXP=10

UVM_INFO scoreboard.sv(145) @ 417: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT= 9, EXP= 9

UVM_INFO scoreboard.sv(145) @ 421: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT= 9, EXP= 9

UVM_INFO sequence.sv(17) @ 423: reporter@@test_seq [BASE_SEQ] Inside Constructor!

UVM_INFO sequence.sv(61) @ 423: reporter@@test_seq [TEST_SEQ] Inside Constructor!

UVM_INFO sequence.sv(69) @ 423: uvm_test_top.env.agnt.seqr@@test_seq [TEST_SEQ] Inside body task!

UVM_INFO scoreboard.sv(145) @ 425: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT= 9, EXP= 9

UVM_INFO scoreboard.sv(145) @ 429: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT=10, EXP=10

UVM_INFO scoreboard.sv(145) @ 433: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT=10, EXP=10

UVM_INFO sequence.sv(17) @ 435: reporter@@test_seq [BASE_SEQ] Inside Constructor!

UVM_INFO sequence.sv(61) @ 435: reporter@@test_seq [TEST_SEQ] Inside Constructor!

UVM_INFO sequence.sv(69) @ 435: uvm_test_top.env.agnt.seqr@@test_seq [TEST_SEQ] Inside body task!

UVM_INFO scoreboard.sv(145) @ 437: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT=10, EXP=10

UVM_INFO scoreboard.sv(145) @ 441: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT= 9, EXP= 9

UVM_INFO scoreboard.sv(145) @ 445: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT= 9, EXP= 9

UVM_INFO sequence.sv(17) @ 447: reporter@@test_seq [BASE_SEQ] Inside Constructor!

UVM_INFO sequence.sv(61) @ 447: reporter@@test_seq [TEST_SEQ] Inside Constructor!

UVM_INFO sequence.sv(69) @ 447: uvm_test_top.env.agnt.seqr@@test_seq [TEST_SEQ] Inside body task!

UVM_INFO scoreboard.sv(145) @ 449: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT= 9, EXP= 9

UVM_INFO scoreboard.sv(145) @ 453: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT=15, EXP=15

UVM_INFO scoreboard.sv(145) @ 457: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT=15, EXP=15

UVM_INFO sequence.sv(17) @ 459: reporter@@test_seq [BASE_SEQ] Inside Constructor!

UVM_INFO sequence.sv(61) @ 459: reporter@@test_seq [TEST_SEQ] Inside Constructor!

UVM_INFO sequence.sv(69) @ 459: uvm_test_top.env.agnt.seqr@@test_seq [TEST_SEQ] Inside body task!

UVM_INFO scoreboard.sv(145) @ 461: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT=15, EXP=15

UVM_INFO scoreboard.sv(145) @ 465: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT= 8, EXP= 8

UVM_INFO scoreboard.sv(145) @ 469: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT= 8, EXP= 8

UVM_INFO sequence.sv(17) @ 471: reporter@@test_seq [BASE_SEQ] Inside Constructor!

UVM_INFO sequence.sv(61) @ 471: reporter@@test_seq [TEST_SEQ] Inside Constructor!

UVM_INFO sequence.sv(69) @ 471: uvm_test_top.env.agnt.seqr@@test_seq [TEST_SEQ] Inside body task!

UVM_INFO scoreboard.sv(145) @ 473: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT= 8, EXP= 8

UVM_INFO scoreboard.sv(145) @ 477: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT=14, EXP=14

UVM_INFO scoreboard.sv(145) @ 481: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT=14, EXP=14

UVM_INFO sequence.sv(17) @ 483: reporter@@test_seq [BASE_SEQ] Inside Constructor!

UVM_INFO sequence.sv(61) @ 483: reporter@@test_seq [TEST_SEQ] Inside Constructor!

UVM_INFO sequence.sv(69) @ 483: uvm_test_top.env.agnt.seqr@@test_seq [TEST_SEQ] Inside body task!

UVM_INFO scoreboard.sv(145) @ 485: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT=14, EXP=14

UVM_INFO scoreboard.sv(145) @ 489: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT= 6, EXP= 6

UVM_INFO scoreboard.sv(145) @ 493: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT= 6, EXP= 6

UVM_INFO sequence.sv(17) @ 495: reporter@@test_seq [BASE_SEQ] Inside Constructor!

UVM_INFO sequence.sv(61) @ 495: reporter@@test_seq [TEST_SEQ] Inside Constructor!

UVM_INFO sequence.sv(69) @ 495: uvm_test_top.env.agnt.seqr@@test_seq [TEST_SEQ] Inside body task!

UVM_INFO scoreboard.sv(145) @ 497: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT= 6, EXP= 6

UVM_INFO scoreboard.sv(145) @ 501: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT= 0, EXP= 0

UVM_INFO scoreboard.sv(145) @ 505: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT= 0, EXP= 0

UVM_INFO sequence.sv(17) @ 507: reporter@@test_seq [BASE_SEQ] Inside Constructor!

UVM_INFO sequence.sv(61) @ 507: reporter@@test_seq [TEST_SEQ] Inside Constructor!

UVM_INFO sequence.sv(69) @ 507: uvm_test_top.env.agnt.seqr@@test_seq [TEST_SEQ] Inside body task!

UVM_INFO scoreboard.sv(145) @ 509: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT= 0, EXP= 0

UVM_INFO scoreboard.sv(145) @ 513: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT= 8, EXP= 8

UVM_INFO scoreboard.sv(145) @ 517: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT= 8, EXP= 8

UVM_INFO sequence.sv(17) @ 519: reporter@@test_seq [BASE_SEQ] Inside Constructor!

UVM_INFO sequence.sv(61) @ 519: reporter@@test_seq [TEST_SEQ] Inside Constructor!

UVM_INFO sequence.sv(69) @ 519: uvm_test_top.env.agnt.seqr@@test_seq [TEST_SEQ] Inside body task!

UVM_INFO scoreboard.sv(145) @ 521: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT= 8, EXP= 8

UVM_INFO scoreboard.sv(145) @ 525: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT= 5, EXP= 5

UVM_INFO scoreboard.sv(145) @ 529: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT= 5, EXP= 5

UVM_INFO sequence.sv(17) @ 531: reporter@@test_seq [BASE_SEQ] Inside Constructor!

UVM_INFO sequence.sv(61) @ 531: reporter@@test_seq [TEST_SEQ] Inside Constructor!

UVM_INFO sequence.sv(69) @ 531: uvm_test_top.env.agnt.seqr@@test_seq [TEST_SEQ] Inside body task!

UVM_INFO scoreboard.sv(145) @ 533: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT= 5, EXP= 5

UVM_INFO scoreboard.sv(145) @ 537: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT= 7, EXP= 7

UVM_INFO scoreboard.sv(145) @ 541: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT= 7, EXP= 7

UVM_INFO sequence.sv(17) @ 543: reporter@@test_seq [BASE_SEQ] Inside Constructor!

UVM_INFO sequence.sv(61) @ 543: reporter@@test_seq [TEST_SEQ] Inside Constructor!

UVM_INFO sequence.sv(69) @ 543: uvm_test_top.env.agnt.seqr@@test_seq [TEST_SEQ] Inside body task!

UVM_INFO scoreboard.sv(145) @ 545: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT= 7, EXP= 7

UVM_INFO scoreboard.sv(145) @ 549: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT=12, EXP=12

UVM_INFO scoreboard.sv(145) @ 553: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT=12, EXP=12

UVM_INFO sequence.sv(17) @ 555: reporter@@test_seq [BASE_SEQ] Inside Constructor!

UVM_INFO sequence.sv(61) @ 555: reporter@@test_seq [TEST_SEQ] Inside Constructor!

UVM_INFO sequence.sv(69) @ 555: uvm_test_top.env.agnt.seqr@@test_seq [TEST_SEQ] Inside body task!

UVM_INFO scoreboard.sv(145) @ 557: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT=12, EXP=12

UVM_INFO scoreboard.sv(145) @ 561: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT= 4, EXP= 4

UVM_INFO scoreboard.sv(145) @ 565: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT= 4, EXP= 4

UVM_INFO sequence.sv(17) @ 567: reporter@@test_seq [BASE_SEQ] Inside Constructor!

UVM_INFO sequence.sv(61) @ 567: reporter@@test_seq [TEST_SEQ] Inside Constructor!

UVM_INFO sequence.sv(69) @ 567: uvm_test_top.env.agnt.seqr@@test_seq [TEST_SEQ] Inside body task!

UVM_INFO scoreboard.sv(145) @ 569: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT= 4, EXP= 4

UVM_INFO scoreboard.sv(145) @ 573: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT= 6, EXP= 6

UVM_INFO scoreboard.sv(145) @ 577: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT= 6, EXP= 6

UVM_INFO sequence.sv(17) @ 579: reporter@@test_seq [BASE_SEQ] Inside Constructor!

UVM_INFO sequence.sv(61) @ 579: reporter@@test_seq [TEST_SEQ] Inside Constructor!

UVM_INFO sequence.sv(69) @ 579: uvm_test_top.env.agnt.seqr@@test_seq [TEST_SEQ] Inside body task!

UVM_INFO scoreboard.sv(145) @ 581: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT= 6, EXP= 6

UVM_INFO scoreboard.sv(145) @ 585: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT= 5, EXP= 5

UVM_INFO scoreboard.sv(145) @ 589: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT= 5, EXP= 5

UVM_INFO sequence.sv(17) @ 591: reporter@@test_seq [BASE_SEQ] Inside Constructor!

UVM_INFO sequence.sv(61) @ 591: reporter@@test_seq [TEST_SEQ] Inside Constructor!

UVM_INFO sequence.sv(69) @ 591: uvm_test_top.env.agnt.seqr@@test_seq [TEST_SEQ] Inside body task!

UVM_INFO scoreboard.sv(145) @ 593: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT= 5, EXP= 5

UVM_INFO scoreboard.sv(145) @ 597: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT= 3, EXP= 3

UVM_INFO scoreboard.sv(145) @ 601: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT= 3, EXP= 3

UVM_INFO sequence.sv(17) @ 603: reporter@@test_seq [BASE_SEQ] Inside Constructor!

UVM_INFO sequence.sv(61) @ 603: reporter@@test_seq [TEST_SEQ] Inside Constructor!

UVM_INFO sequence.sv(69) @ 603: uvm_test_top.env.agnt.seqr@@test_seq [TEST_SEQ] Inside body task!

UVM_INFO scoreboard.sv(145) @ 605: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT= 3, EXP= 3

UVM_INFO scoreboard.sv(145) @ 609: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT=14, EXP=14

UVM_INFO scoreboard.sv(145) @ 613: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT=14, EXP=14

UVM_INFO sequence.sv(17) @ 615: reporter@@test_seq [BASE_SEQ] Inside Constructor!

UVM_INFO sequence.sv(61) @ 615: reporter@@test_seq [TEST_SEQ] Inside Constructor!

UVM_INFO sequence.sv(69) @ 615: uvm_test_top.env.agnt.seqr@@test_seq [TEST_SEQ] Inside body task!

UVM_INFO scoreboard.sv(145) @ 617: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT=14, EXP=14

UVM_INFO scoreboard.sv(145) @ 621: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT=15, EXP=15

UVM_INFO scoreboard.sv(145) @ 625: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT=15, EXP=15

UVM_INFO sequence.sv(17) @ 627: reporter@@test_seq [BASE_SEQ] Inside Constructor!

UVM_INFO sequence.sv(61) @ 627: reporter@@test_seq [TEST_SEQ] Inside Constructor!

UVM_INFO sequence.sv(69) @ 627: uvm_test_top.env.agnt.seqr@@test_seq [TEST_SEQ] Inside body task!

UVM_INFO scoreboard.sv(145) @ 629: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT=15, EXP=15

UVM_INFO scoreboard.sv(145) @ 633: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT=14, EXP=14

UVM_INFO scoreboard.sv(145) @ 637: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT=14, EXP=14

UVM_INFO sequence.sv(17) @ 639: reporter@@test_seq [BASE_SEQ] Inside Constructor!

UVM_INFO sequence.sv(61) @ 639: reporter@@test_seq [TEST_SEQ] Inside Constructor!

UVM_INFO sequence.sv(69) @ 639: uvm_test_top.env.agnt.seqr@@test_seq [TEST_SEQ] Inside body task!

UVM_INFO scoreboard.sv(145) @ 641: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT=14, EXP=14

UVM_INFO scoreboard.sv(145) @ 645: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT=15, EXP=15

UVM_INFO scoreboard.sv(145) @ 649: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT=15, EXP=15

UVM_INFO sequence.sv(17) @ 651: reporter@@test_seq [BASE_SEQ] Inside Constructor!

UVM_INFO sequence.sv(61) @ 651: reporter@@test_seq [TEST_SEQ] Inside Constructor!

UVM_INFO sequence.sv(69) @ 651: uvm_test_top.env.agnt.seqr@@test_seq [TEST_SEQ] Inside body task!

UVM_INFO scoreboard.sv(145) @ 653: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT=15, EXP=15

UVM_INFO scoreboard.sv(145) @ 657: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT= 2, EXP= 2

UVM_INFO scoreboard.sv(145) @ 661: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT= 2, EXP= 2

UVM_INFO sequence.sv(17) @ 663: reporter@@test_seq [BASE_SEQ] Inside Constructor!

UVM_INFO sequence.sv(61) @ 663: reporter@@test_seq [TEST_SEQ] Inside Constructor!

UVM_INFO sequence.sv(69) @ 663: uvm_test_top.env.agnt.seqr@@test_seq [TEST_SEQ] Inside body task!

UVM_INFO scoreboard.sv(145) @ 665: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT= 2, EXP= 2

UVM_INFO scoreboard.sv(145) @ 669: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT= 9, EXP= 9

UVM_INFO scoreboard.sv(145) @ 673: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT= 9, EXP= 9

UVM_INFO sequence.sv(17) @ 675: reporter@@test_seq [BASE_SEQ] Inside Constructor!

UVM_INFO sequence.sv(61) @ 675: reporter@@test_seq [TEST_SEQ] Inside Constructor!

UVM_INFO sequence.sv(69) @ 675: uvm_test_top.env.agnt.seqr@@test_seq [TEST_SEQ] Inside body task!

UVM_INFO scoreboard.sv(145) @ 677: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT= 9, EXP= 9

UVM_INFO scoreboard.sv(145) @ 681: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT= 3, EXP= 3

UVM_INFO scoreboard.sv(145) @ 685: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT= 3, EXP= 3

UVM_INFO sequence.sv(17) @ 687: reporter@@test_seq [BASE_SEQ] Inside Constructor!

UVM_INFO sequence.sv(61) @ 687: reporter@@test_seq [TEST_SEQ] Inside Constructor!

UVM_INFO sequence.sv(69) @ 687: uvm_test_top.env.agnt.seqr@@test_seq [TEST_SEQ] Inside body task!

UVM_INFO scoreboard.sv(145) @ 689: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT= 3, EXP= 3

UVM_INFO scoreboard.sv(145) @ 693: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT= 2, EXP= 2

UVM_INFO scoreboard.sv(145) @ 697: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT= 2, EXP= 2

UVM_INFO sequence.sv(17) @ 699: reporter@@test_seq [BASE_SEQ] Inside Constructor!

UVM_INFO sequence.sv(61) @ 699: reporter@@test_seq [TEST_SEQ] Inside Constructor!

UVM_INFO sequence.sv(69) @ 699: uvm_test_top.env.agnt.seqr@@test_seq [TEST_SEQ] Inside body task!

UVM_INFO scoreboard.sv(145) @ 701: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT= 2, EXP= 2

UVM_INFO scoreboard.sv(145) @ 705: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT= 1, EXP= 1

UVM_INFO scoreboard.sv(145) @ 709: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT= 1, EXP= 1

UVM_INFO sequence.sv(17) @ 711: reporter@@test_seq [BASE_SEQ] Inside Constructor!

UVM_INFO sequence.sv(61) @ 711: reporter@@test_seq [TEST_SEQ] Inside Constructor!

UVM_INFO sequence.sv(69) @ 711: uvm_test_top.env.agnt.seqr@@test_seq [TEST_SEQ] Inside body task!

UVM_INFO scoreboard.sv(145) @ 713: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT= 1, EXP= 1

UVM_INFO scoreboard.sv(145) @ 717: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT= 7, EXP= 7

UVM_INFO scoreboard.sv(145) @ 721: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT= 7, EXP= 7

UVM_INFO sequence.sv(17) @ 723: reporter@@test_seq [BASE_SEQ] Inside Constructor!

UVM_INFO sequence.sv(61) @ 723: reporter@@test_seq [TEST_SEQ] Inside Constructor!

UVM_INFO sequence.sv(69) @ 723: uvm_test_top.env.agnt.seqr@@test_seq [TEST_SEQ] Inside body task!

UVM_INFO scoreboard.sv(145) @ 725: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT= 7, EXP= 7

UVM_INFO scoreboard.sv(145) @ 729: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT= 8, EXP= 8

UVM_INFO scoreboard.sv(145) @ 733: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT= 8, EXP= 8

UVM_INFO sequence.sv(17) @ 735: reporter@@test_seq [BASE_SEQ] Inside Constructor!

UVM_INFO sequence.sv(61) @ 735: reporter@@test_seq [TEST_SEQ] Inside Constructor!

UVM_INFO sequence.sv(69) @ 735: uvm_test_top.env.agnt.seqr@@test_seq [TEST_SEQ] Inside body task!

UVM_INFO scoreboard.sv(145) @ 737: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT= 8, EXP= 8

UVM_INFO scoreboard.sv(145) @ 741: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT= 6, EXP= 6

UVM_INFO scoreboard.sv(145) @ 745: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT= 6, EXP= 6

UVM_INFO sequence.sv(17) @ 747: reporter@@test_seq [BASE_SEQ] Inside Constructor!

UVM_INFO sequence.sv(61) @ 747: reporter@@test_seq [TEST_SEQ] Inside Constructor!

UVM_INFO sequence.sv(69) @ 747: uvm_test_top.env.agnt.seqr@@test_seq [TEST_SEQ] Inside body task!

UVM_INFO scoreboard.sv(145) @ 749: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT= 6, EXP= 6

UVM_INFO scoreboard.sv(145) @ 753: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT= 9, EXP= 9

UVM_INFO scoreboard.sv(145) @ 757: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT= 9, EXP= 9

UVM_INFO sequence.sv(17) @ 759: reporter@@test_seq [BASE_SEQ] Inside Constructor!

UVM_INFO sequence.sv(61) @ 759: reporter@@test_seq [TEST_SEQ] Inside Constructor!

UVM_INFO sequence.sv(69) @ 759: uvm_test_top.env.agnt.seqr@@test_seq [TEST_SEQ] Inside body task!

UVM_INFO scoreboard.sv(145) @ 761: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT= 9, EXP= 9

UVM_INFO scoreboard.sv(145) @ 765: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT= 5, EXP= 5

UVM_INFO scoreboard.sv(145) @ 769: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT= 5, EXP= 5

UVM_INFO sequence.sv(17) @ 771: reporter@@test_seq [BASE_SEQ] Inside Constructor!

UVM_INFO sequence.sv(61) @ 771: reporter@@test_seq [TEST_SEQ] Inside Constructor!

UVM_INFO sequence.sv(69) @ 771: uvm_test_top.env.agnt.seqr@@test_seq [TEST_SEQ] Inside body task!

UVM_INFO scoreboard.sv(145) @ 773: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT= 5, EXP= 5

UVM_INFO scoreboard.sv(145) @ 777: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT= 0, EXP= 0

UVM_INFO scoreboard.sv(145) @ 781: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT= 0, EXP= 0

UVM_INFO sequence.sv(17) @ 783: reporter@@test_seq [BASE_SEQ] Inside Constructor!

UVM_INFO sequence.sv(61) @ 783: reporter@@test_seq [TEST_SEQ] Inside Constructor!

UVM_INFO sequence.sv(69) @ 783: uvm_test_top.env.agnt.seqr@@test_seq [TEST_SEQ] Inside body task!

UVM_INFO scoreboard.sv(145) @ 785: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT= 0, EXP= 0

UVM_INFO scoreboard.sv(145) @ 789: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT=11, EXP=11

UVM_INFO scoreboard.sv(145) @ 793: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT=11, EXP=11

UVM_INFO sequence.sv(17) @ 795: reporter@@test_seq [BASE_SEQ] Inside Constructor!

UVM_INFO sequence.sv(61) @ 795: reporter@@test_seq [TEST_SEQ] Inside Constructor!

UVM_INFO sequence.sv(69) @ 795: uvm_test_top.env.agnt.seqr@@test_seq [TEST_SEQ] Inside body task!

UVM_INFO scoreboard.sv(145) @ 797: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT=11, EXP=11

UVM_INFO scoreboard.sv(145) @ 801: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT= 6, EXP= 6

UVM_INFO scoreboard.sv(145) @ 805: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT= 6, EXP= 6

UVM_INFO sequence.sv(17) @ 807: reporter@@test_seq [BASE_SEQ] Inside Constructor!

UVM_INFO sequence.sv(61) @ 807: reporter@@test_seq [TEST_SEQ] Inside Constructor!

UVM_INFO sequence.sv(69) @ 807: uvm_test_top.env.agnt.seqr@@test_seq [TEST_SEQ] Inside body task!

UVM_INFO scoreboard.sv(145) @ 809: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT= 6, EXP= 6

UVM_INFO scoreboard.sv(145) @ 813: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT=12, EXP=12

UVM_INFO scoreboard.sv(145) @ 817: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT=12, EXP=12

UVM_INFO sequence.sv(17) @ 819: reporter@@test_seq [BASE_SEQ] Inside Constructor!

UVM_INFO sequence.sv(61) @ 819: reporter@@test_seq [TEST_SEQ] Inside Constructor!

UVM_INFO sequence.sv(69) @ 819: uvm_test_top.env.agnt.seqr@@test_seq [TEST_SEQ] Inside body task!

UVM_INFO scoreboard.sv(145) @ 821: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT=12, EXP=12

UVM_INFO scoreboard.sv(145) @ 825: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT= 5, EXP= 5

UVM_INFO scoreboard.sv(145) @ 829: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT= 5, EXP= 5

UVM_INFO sequence.sv(17) @ 831: reporter@@test_seq [BASE_SEQ] Inside Constructor!

UVM_INFO sequence.sv(61) @ 831: reporter@@test_seq [TEST_SEQ] Inside Constructor!

UVM_INFO sequence.sv(69) @ 831: uvm_test_top.env.agnt.seqr@@test_seq [TEST_SEQ] Inside body task!

UVM_INFO scoreboard.sv(145) @ 833: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT= 5, EXP= 5

UVM_INFO scoreboard.sv(145) @ 837: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT= 4, EXP= 4

UVM_INFO scoreboard.sv(145) @ 841: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT= 4, EXP= 4

UVM_INFO sequence.sv(17) @ 843: reporter@@test_seq [BASE_SEQ] Inside Constructor!

UVM_INFO sequence.sv(61) @ 843: reporter@@test_seq [TEST_SEQ] Inside Constructor!

UVM_INFO sequence.sv(69) @ 843: uvm_test_top.env.agnt.seqr@@test_seq [TEST_SEQ] Inside body task!

UVM_INFO scoreboard.sv(145) @ 845: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT= 4, EXP= 4

UVM_INFO scoreboard.sv(145) @ 849: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT= 1, EXP= 1

UVM_INFO scoreboard.sv(145) @ 853: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT= 1, EXP= 1

UVM_INFO sequence.sv(17) @ 855: reporter@@test_seq [BASE_SEQ] Inside Constructor!

UVM_INFO sequence.sv(61) @ 855: reporter@@test_seq [TEST_SEQ] Inside Constructor!

UVM_INFO sequence.sv(69) @ 855: uvm_test_top.env.agnt.seqr@@test_seq [TEST_SEQ] Inside body task!

UVM_INFO scoreboard.sv(145) @ 857: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT= 1, EXP= 1

UVM_INFO scoreboard.sv(145) @ 861: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT=11, EXP=11

UVM_INFO scoreboard.sv(145) @ 865: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT=11, EXP=11

UVM_INFO sequence.sv(17) @ 867: reporter@@test_seq [BASE_SEQ] Inside Constructor!

UVM_INFO sequence.sv(61) @ 867: reporter@@test_seq [TEST_SEQ] Inside Constructor!

UVM_INFO sequence.sv(69) @ 867: uvm_test_top.env.agnt.seqr@@test_seq [TEST_SEQ] Inside body task!

UVM_INFO scoreboard.sv(145) @ 869: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT=11, EXP=11

UVM_INFO scoreboard.sv(145) @ 873: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT= 1, EXP= 1

UVM_INFO scoreboard.sv(145) @ 877: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT= 1, EXP= 1

UVM_INFO sequence.sv(17) @ 879: reporter@@test_seq [BASE_SEQ] Inside Constructor!

UVM_INFO sequence.sv(61) @ 879: reporter@@test_seq [TEST_SEQ] Inside Constructor!

UVM_INFO sequence.sv(69) @ 879: uvm_test_top.env.agnt.seqr@@test_seq [TEST_SEQ] Inside body task!

UVM_INFO scoreboard.sv(145) @ 881: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT= 1, EXP= 1

UVM_INFO scoreboard.sv(145) @ 885: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT= 4, EXP= 4

UVM_INFO scoreboard.sv(145) @ 889: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT= 4, EXP= 4

UVM_INFO sequence.sv(17) @ 891: reporter@@test_seq [BASE_SEQ] Inside Constructor!

UVM_INFO sequence.sv(61) @ 891: reporter@@test_seq [TEST_SEQ] Inside Constructor!

UVM_INFO sequence.sv(69) @ 891: uvm_test_top.env.agnt.seqr@@test_seq [TEST_SEQ] Inside body task!

UVM_INFO scoreboard.sv(145) @ 893: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT= 4, EXP= 4

UVM_INFO scoreboard.sv(145) @ 897: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT= 2, EXP= 2

UVM_INFO scoreboard.sv(145) @ 901: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT= 2, EXP= 2

UVM_INFO sequence.sv(17) @ 903: reporter@@test_seq [BASE_SEQ] Inside Constructor!

UVM_INFO sequence.sv(61) @ 903: reporter@@test_seq [TEST_SEQ] Inside Constructor!

UVM_INFO sequence.sv(69) @ 903: uvm_test_top.env.agnt.seqr@@test_seq [TEST_SEQ] Inside body task!

UVM_INFO scoreboard.sv(145) @ 905: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT= 2, EXP= 2

UVM_INFO scoreboard.sv(145) @ 909: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT=14, EXP=14

UVM_INFO scoreboard.sv(145) @ 913: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT=14, EXP=14

UVM_INFO sequence.sv(17) @ 915: reporter@@test_seq [BASE_SEQ] Inside Constructor!

UVM_INFO sequence.sv(61) @ 915: reporter@@test_seq [TEST_SEQ] Inside Constructor!

UVM_INFO sequence.sv(69) @ 915: uvm_test_top.env.agnt.seqr@@test_seq [TEST_SEQ] Inside body task!

UVM_INFO scoreboard.sv(145) @ 917: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT=14, EXP=14

UVM_INFO scoreboard.sv(145) @ 921: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT= 9, EXP= 9

UVM_INFO scoreboard.sv(145) @ 925: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT= 9, EXP= 9

UVM_INFO sequence.sv(17) @ 927: reporter@@test_seq [BASE_SEQ] Inside Constructor!

UVM_INFO sequence.sv(61) @ 927: reporter@@test_seq [TEST_SEQ] Inside Constructor!

UVM_INFO sequence.sv(69) @ 927: uvm_test_top.env.agnt.seqr@@test_seq [TEST_SEQ] Inside body task!

UVM_INFO scoreboard.sv(145) @ 929: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT= 9, EXP= 9

UVM_INFO scoreboard.sv(145) @ 933: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT= 4, EXP= 4

UVM_INFO scoreboard.sv(145) @ 937: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT= 4, EXP= 4

UVM_INFO sequence.sv(17) @ 939: reporter@@test_seq [BASE_SEQ] Inside Constructor!

UVM_INFO sequence.sv(61) @ 939: reporter@@test_seq [TEST_SEQ] Inside Constructor!

UVM_INFO sequence.sv(69) @ 939: uvm_test_top.env.agnt.seqr@@test_seq [TEST_SEQ] Inside body task!

UVM_INFO scoreboard.sv(145) @ 941: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT= 4, EXP= 4

UVM_INFO scoreboard.sv(145) @ 945: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT=12, EXP=12

UVM_INFO scoreboard.sv(145) @ 949: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT=12, EXP=12

UVM_INFO sequence.sv(17) @ 951: reporter@@test_seq [BASE_SEQ] Inside Constructor!

UVM_INFO sequence.sv(61) @ 951: reporter@@test_seq [TEST_SEQ] Inside Constructor!

UVM_INFO sequence.sv(69) @ 951: uvm_test_top.env.agnt.seqr@@test_seq [TEST_SEQ] Inside body task!

UVM_INFO scoreboard.sv(145) @ 953: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT=12, EXP=12

UVM_INFO scoreboard.sv(145) @ 957: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT= 3, EXP= 3

UVM_INFO scoreboard.sv(145) @ 961: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT= 3, EXP= 3

UVM_INFO sequence.sv(17) @ 963: reporter@@test_seq [BASE_SEQ] Inside Constructor!

UVM_INFO sequence.sv(61) @ 963: reporter@@test_seq [TEST_SEQ] Inside Constructor!

UVM_INFO sequence.sv(69) @ 963: uvm_test_top.env.agnt.seqr@@test_seq [TEST_SEQ] Inside body task!

UVM_INFO scoreboard.sv(145) @ 965: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT= 3, EXP= 3

UVM_INFO scoreboard.sv(145) @ 969: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT= 3, EXP= 3

UVM_INFO scoreboard.sv(145) @ 973: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT= 3, EXP= 3

UVM_INFO sequence.sv(17) @ 975: reporter@@test_seq [BASE_SEQ] Inside Constructor!

UVM_INFO sequence.sv(61) @ 975: reporter@@test_seq [TEST_SEQ] Inside Constructor!

UVM_INFO sequence.sv(69) @ 975: uvm_test_top.env.agnt.seqr@@test_seq [TEST_SEQ] Inside body task!

UVM_INFO scoreboard.sv(145) @ 977: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT= 3, EXP= 3

UVM_INFO scoreboard.sv(145) @ 981: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT=13, EXP=13

UVM_INFO scoreboard.sv(145) @ 985: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT=13, EXP=13

UVM_INFO sequence.sv(17) @ 987: reporter@@test_seq [BASE_SEQ] Inside Constructor!

UVM_INFO sequence.sv(61) @ 987: reporter@@test_seq [TEST_SEQ] Inside Constructor!

UVM_INFO sequence.sv(69) @ 987: uvm_test_top.env.agnt.seqr@@test_seq [TEST_SEQ] Inside body task!

UVM_INFO scoreboard.sv(145) @ 989: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT=13, EXP=13

UVM_INFO scoreboard.sv(145) @ 993: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT=14, EXP=14

UVM_INFO scoreboard.sv(145) @ 997: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT=14, EXP=14

UVM_INFO sequence.sv(17) @ 999: reporter@@test_seq [BASE_SEQ] Inside Constructor!

UVM_INFO sequence.sv(61) @ 999: reporter@@test_seq [TEST_SEQ] Inside Constructor!

UVM_INFO sequence.sv(69) @ 999: uvm_test_top.env.agnt.seqr@@test_seq [TEST_SEQ] Inside body task!

UVM_INFO scoreboard.sv(145) @ 1001: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT=14, EXP=14

UVM_INFO scoreboard.sv(145) @ 1005: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT=11, EXP=11

UVM_INFO scoreboard.sv(145) @ 1009: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT=11, EXP=11

UVM_INFO sequence.sv(17) @ 1011: reporter@@test_seq [BASE_SEQ] Inside Constructor!

UVM_INFO sequence.sv(61) @ 1011: reporter@@test_seq [TEST_SEQ] Inside Constructor!

UVM_INFO sequence.sv(69) @ 1011: uvm_test_top.env.agnt.seqr@@test_seq [TEST_SEQ] Inside body task!

UVM_INFO scoreboard.sv(145) @ 1013: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT=11, EXP=11

UVM_INFO scoreboard.sv(145) @ 1017: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT= 4, EXP= 4

UVM_INFO scoreboard.sv(145) @ 1021: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT= 4, EXP= 4

UVM_INFO sequence.sv(17) @ 1023: reporter@@test_seq [BASE_SEQ] Inside Constructor!

UVM_INFO sequence.sv(61) @ 1023: reporter@@test_seq [TEST_SEQ] Inside Constructor!

UVM_INFO sequence.sv(69) @ 1023: uvm_test_top.env.agnt.seqr@@test_seq [TEST_SEQ] Inside body task!

UVM_INFO scoreboard.sv(145) @ 1025: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT= 4, EXP= 4

UVM_INFO scoreboard.sv(145) @ 1029: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT= 2, EXP= 2

UVM_INFO scoreboard.sv(145) @ 1033: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT= 2, EXP= 2

UVM_INFO sequence.sv(17) @ 1035: reporter@@test_seq [BASE_SEQ] Inside Constructor!

UVM_INFO sequence.sv(61) @ 1035: reporter@@test_seq [TEST_SEQ] Inside Constructor!

UVM_INFO sequence.sv(69) @ 1035: uvm_test_top.env.agnt.seqr@@test_seq [TEST_SEQ] Inside body task!

UVM_INFO scoreboard.sv(145) @ 1037: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT= 2, EXP= 2

UVM_INFO scoreboard.sv(145) @ 1041: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT= 9, EXP= 9

UVM_INFO scoreboard.sv(145) @ 1045: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT= 9, EXP= 9

UVM_INFO sequence.sv(17) @ 1047: reporter@@test_seq [BASE_SEQ] Inside Constructor!

UVM_INFO sequence.sv(61) @ 1047: reporter@@test_seq [TEST_SEQ] Inside Constructor!

UVM_INFO sequence.sv(69) @ 1047: uvm_test_top.env.agnt.seqr@@test_seq [TEST_SEQ] Inside body task!

UVM_INFO scoreboard.sv(145) @ 1049: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT= 9, EXP= 9

UVM_INFO scoreboard.sv(145) @ 1053: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT= 3, EXP= 3

UVM_INFO scoreboard.sv(145) @ 1057: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT= 3, EXP= 3

UVM_INFO sequence.sv(17) @ 1059: reporter@@test_seq [BASE_SEQ] Inside Constructor!

UVM_INFO sequence.sv(61) @ 1059: reporter@@test_seq [TEST_SEQ] Inside Constructor!

UVM_INFO sequence.sv(69) @ 1059: uvm_test_top.env.agnt.seqr@@test_seq [TEST_SEQ] Inside body task!

UVM_INFO scoreboard.sv(145) @ 1061: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT= 3, EXP= 3

UVM_INFO scoreboard.sv(145) @ 1065: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT= 3, EXP= 3

UVM_INFO scoreboard.sv(145) @ 1069: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT= 3, EXP= 3

UVM_INFO sequence.sv(17) @ 1071: reporter@@test_seq [BASE_SEQ] Inside Constructor!

UVM_INFO sequence.sv(61) @ 1071: reporter@@test_seq [TEST_SEQ] Inside Constructor!

UVM_INFO sequence.sv(69) @ 1071: uvm_test_top.env.agnt.seqr@@test_seq [TEST_SEQ] Inside body task!

UVM_INFO scoreboard.sv(145) @ 1073: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT= 3, EXP= 3

UVM_INFO scoreboard.sv(145) @ 1077: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT= 5, EXP= 5

UVM_INFO scoreboard.sv(145) @ 1081: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT= 5, EXP= 5

UVM_INFO sequence.sv(17) @ 1083: reporter@@test_seq [BASE_SEQ] Inside Constructor!

UVM_INFO sequence.sv(61) @ 1083: reporter@@test_seq [TEST_SEQ] Inside Constructor!

UVM_INFO sequence.sv(69) @ 1083: uvm_test_top.env.agnt.seqr@@test_seq [TEST_SEQ] Inside body task!

UVM_INFO scoreboard.sv(145) @ 1085: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT= 5, EXP= 5

UVM_INFO scoreboard.sv(145) @ 1089: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT= 4, EXP= 4

UVM_INFO scoreboard.sv(145) @ 1093: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT= 4, EXP= 4

UVM_INFO sequence.sv(17) @ 1095: reporter@@test_seq [BASE_SEQ] Inside Constructor!

UVM_INFO sequence.sv(61) @ 1095: reporter@@test_seq [TEST_SEQ] Inside Constructor!

UVM_INFO sequence.sv(69) @ 1095: uvm_test_top.env.agnt.seqr@@test_seq [TEST_SEQ] Inside body task!

UVM_INFO scoreboard.sv(145) @ 1097: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT= 4, EXP= 4

UVM_INFO scoreboard.sv(145) @ 1101: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT= 1, EXP= 1

UVM_INFO scoreboard.sv(145) @ 1105: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT= 1, EXP= 1

UVM_INFO sequence.sv(17) @ 1107: reporter@@test_seq [BASE_SEQ] Inside Constructor!

UVM_INFO sequence.sv(61) @ 1107: reporter@@test_seq [TEST_SEQ] Inside Constructor!

UVM_INFO sequence.sv(69) @ 1107: uvm_test_top.env.agnt.seqr@@test_seq [TEST_SEQ] Inside body task!

UVM_INFO scoreboard.sv(145) @ 1109: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT= 1, EXP= 1

UVM_INFO scoreboard.sv(145) @ 1113: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT= 0, EXP= 0

UVM_INFO scoreboard.sv(145) @ 1117: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT= 0, EXP= 0

UVM_INFO sequence.sv(17) @ 1119: reporter@@test_seq [BASE_SEQ] Inside Constructor!

UVM_INFO sequence.sv(61) @ 1119: reporter@@test_seq [TEST_SEQ] Inside Constructor!

UVM_INFO sequence.sv(69) @ 1119: uvm_test_top.env.agnt.seqr@@test_seq [TEST_SEQ] Inside body task!

UVM_INFO scoreboard.sv(145) @ 1121: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT= 0, EXP= 0

UVM_INFO scoreboard.sv(145) @ 1125: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT= 9, EXP= 9

UVM_INFO scoreboard.sv(145) @ 1129: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT= 9, EXP= 9

UVM_INFO sequence.sv(17) @ 1131: reporter@@test_seq [BASE_SEQ] Inside Constructor!

UVM_INFO sequence.sv(61) @ 1131: reporter@@test_seq [TEST_SEQ] Inside Constructor!

UVM_INFO sequence.sv(69) @ 1131: uvm_test_top.env.agnt.seqr@@test_seq [TEST_SEQ] Inside body task!

UVM_INFO scoreboard.sv(145) @ 1133: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT= 9, EXP= 9

UVM_INFO scoreboard.sv(145) @ 1137: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT=11, EXP=11

UVM_INFO scoreboard.sv(145) @ 1141: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT=11, EXP=11

UVM_INFO sequence.sv(17) @ 1143: reporter@@test_seq [BASE_SEQ] Inside Constructor!

UVM_INFO sequence.sv(61) @ 1143: reporter@@test_seq [TEST_SEQ] Inside Constructor!

UVM_INFO sequence.sv(69) @ 1143: uvm_test_top.env.agnt.seqr@@test_seq [TEST_SEQ] Inside body task!

UVM_INFO scoreboard.sv(145) @ 1145: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT=11, EXP=11

UVM_INFO scoreboard.sv(145) @ 1149: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT= 2, EXP= 2

UVM_INFO scoreboard.sv(145) @ 1153: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT= 2, EXP= 2

UVM_INFO sequence.sv(17) @ 1155: reporter@@test_seq [BASE_SEQ] Inside Constructor!

UVM_INFO sequence.sv(61) @ 1155: reporter@@test_seq [TEST_SEQ] Inside Constructor!

UVM_INFO sequence.sv(69) @ 1155: uvm_test_top.env.agnt.seqr@@test_seq [TEST_SEQ] Inside body task!

UVM_INFO scoreboard.sv(145) @ 1157: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT= 2, EXP= 2

UVM_INFO scoreboard.sv(145) @ 1161: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT=11, EXP=11

UVM_INFO scoreboard.sv(145) @ 1165: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT=11, EXP=11

UVM_INFO sequence.sv(17) @ 1167: reporter@@test_seq [BASE_SEQ] Inside Constructor!

UVM_INFO sequence.sv(61) @ 1167: reporter@@test_seq [TEST_SEQ] Inside Constructor!

UVM_INFO sequence.sv(69) @ 1167: uvm_test_top.env.agnt.seqr@@test_seq [TEST_SEQ] Inside body task!

UVM_INFO scoreboard.sv(145) @ 1169: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT=11, EXP=11

UVM_INFO scoreboard.sv(145) @ 1173: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT= 5, EXP= 5

UVM_INFO scoreboard.sv(145) @ 1177: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT= 5, EXP= 5

UVM_INFO sequence.sv(17) @ 1179: reporter@@test_seq [BASE_SEQ] Inside Constructor!

UVM_INFO sequence.sv(61) @ 1179: reporter@@test_seq [TEST_SEQ] Inside Constructor!

UVM_INFO sequence.sv(69) @ 1179: uvm_test_top.env.agnt.seqr@@test_seq [TEST_SEQ] Inside body task!

UVM_INFO scoreboard.sv(145) @ 1181: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT= 5, EXP= 5

UVM_INFO scoreboard.sv(145) @ 1185: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT= 1, EXP= 1

UVM_INFO scoreboard.sv(145) @ 1189: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT= 1, EXP= 1

UVM_INFO sequence.sv(17) @ 1191: reporter@@test_seq [BASE_SEQ] Inside Constructor!

UVM_INFO sequence.sv(61) @ 1191: reporter@@test_seq [TEST_SEQ] Inside Constructor!

UVM_INFO sequence.sv(69) @ 1191: uvm_test_top.env.agnt.seqr@@test_seq [TEST_SEQ] Inside body task!

UVM_INFO scoreboard.sv(145) @ 1193: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT= 1, EXP= 1

UVM_INFO scoreboard.sv(145) @ 1197: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT= 0, EXP= 0

UVM_INFO scoreboard.sv(145) @ 1201: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT= 0, EXP= 0

UVM_INFO sequence.sv(17) @ 1203: reporter@@test_seq [BASE_SEQ] Inside Constructor!

UVM_INFO sequence.sv(61) @ 1203: reporter@@test_seq [TEST_SEQ] Inside Constructor!

UVM_INFO sequence.sv(69) @ 1203: uvm_test_top.env.agnt.seqr@@test_seq [TEST_SEQ] Inside body task!

UVM_INFO scoreboard.sv(145) @ 1205: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT= 0, EXP= 0

UVM_INFO scoreboard.sv(145) @ 1209: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT=13, EXP=13

UVM_INFO scoreboard.sv(145) @ 1213: uvm_test_top.env.scb [COMPARE] Transaction Passed! ACT=13, EXP=13

UVM_INFO /apps/vcsmx/vcs/S-2021.09//etc/uvm-1.2/src/base/uvm_objection.svh(1276) @ 1215: reporter [TEST_DONE] 'run' phase is ready to proceed to the 'extract' phase

UVM_INFO /apps/vcsmx/vcs/S-2021.09//etc/uvm-1.2/src/base/uvm_report_server.svh(904) @ 1215: reporter [UVM/REPORT/SERVER]

--- UVM Report Summary ---

** Report counts by severity

UVM_INFO :  631

UVM_WARNING :    0

UVM_ERROR :    0

UVM_FATAL :    0

** Report counts by id

[AGENT_CLASS]     4

[BASE_SEQ]   102

[COMPARE]   299

[DRIVER_CLASS]     4

[ENV_CLASS]     4

[MONITOR_CLASS]     4

[RNTST]     1

[SCB_CLASS]     4

[SEQUENCER_CLASS]     3

[TEST_CLASS]     4

[TEST_DONE]     1

[TEST_SEQ]   200

[UVM/RELNOTES]     1

$finish called from file "/apps/vcsmx/vcs/S-2021.09//etc/uvm-1.2/src/base/uvm_root.svh", line 527.

$finish at simulation time                 1215

          V C S   S i m u l a t i o n   R e p o r t

Time: 1215 ns

CPU Time:      0.740 seconds;       Data structure size:   0.3Mb

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