Verilog AMS: DUT and testbench code example: Voltage deadband amplifier using Cadence xrun
Here is an example of a simple Verilog AMS DUT ( Design Under Test ) of Voltage deadband amplifier ( from my previous post Verilog AMS: Code examples) with its simple Verilog AMS testbench infrastructure.
Also here is included all files necessary to run the simulation using Cadence xrun command and an example of a possible file directory structure for developing potentialy multiple Verilog AMS DUT’s
and their respective tests/testbenches.
The files directory structure consists of the following directories :
- DUT_VAMS: where all Verilog AMS DUT’s are kept and in this case there is only one, Voltage deadband amplifier:
- DUT_VAMS/vdba.vams
- TESTBENCH: where all verification infrastructure files are kept including:
- Cadence files necessary to run xrun command, the files that could be shared with multiple Verilog AMS DUT’s and their respective tests/testbenches, such as:
TESTBENCH/cds_globals.vams:
`include "disciplines.vams"
module cds_globals;
ground \gnd! ;
wire \vdd! ;
// Design Variables
dynamicparam real VDD = 1.8;
endmodule
# define the database for the waveforms
database -open waves -into waves.shm -default
# probe all
probe -create -database waves -all -depth all
# run simulation
run 1s
// **************************************************************** // AMS simulation control file for xrun netlist based flow // **************************************************************** simulator lang=spectre // global signals global 0 vdd! // model deck // ams configuration options amsd{ // set the connect rule power supply ie vsup=1.8 } // run a little bit beyond 1s so that simvision // will be active after 1s of transient simulation tran tran stop=1.1 annotate=status
#!/bin/bash
# run_simulation_voltage_deadband_amplifier.tcl
export DUT_VAMS=./../DUT_VAMS/ export TESTBENCH=./../TESTBENCH/ xrun \ $DUT_VAMS/vdba.vams \ $TESTBENCH/top_vol_deadb_amp.vams \ $TESTBENCH/cds_globals.vams \ $TESTBENCH/amscf.scs \ -timescale 1ns/1ns \ -iereport \ -access +rwc \ -input $TESTBENCH/probe.tcl \ -gui
© 2011-2019 ASIC Stoic. All rights reserved
endmodule
- TESTBENCH/probe.tcl:
- TESTBENCH/amscf.scs:
// **************************************************************** // AMS simulation control file for xrun netlist based flow // **************************************************************** simulator lang=spectre // global signals global 0 vdd! // model deck // ams configuration options amsd{ // set the connect rule power supply ie vsup=1.8 } // run a little bit beyond 1s so that simvision // will be active after 1s of transient simulation tran tran stop=1.1 annotate=status
- A simple Voltage deadband amplifier test/testbench:
- TESTBENCH/top_vol_deadb_amp.vams
- VERIFICATION: Verilog AMS simulation of the DUT is run from here, with a simulation script like this:
- VERIFICATION/SCRIPTS/run_simulation_voltage_deadband_amplifier
- Needless to say, the directory VERIFICATION/SCRIPTS could contain all “run simulation” scripts for all DUT’s and in this case it is a home of a “run simulation” script of Voltage deadband
#!/bin/bash
# run_simulation_voltage_deadband_amplifier.tcl
export DUT_VAMS=./../DUT_VAMS/ export TESTBENCH=./../TESTBENCH/ xrun \ $DUT_VAMS/vdba.vams \ $TESTBENCH/top_vol_deadb_amp.vams \ $TESTBENCH/cds_globals.vams \ $TESTBENCH/amscf.scs \ -timescale 1ns/1ns \ -iereport \ -access +rwc \ -input $TESTBENCH/probe.tcl \ -gui
Here is a summary of all the files and their respective directories in this example (all the files are included in this post Verilog_AMS_VDBA.zip ):
./TESTBENCH/cds_globals.vams
./TESTBENCH/probe.tcl
./TESTBENCH/amscf.scs
./TESTBENCH/top_vol_deadb_amp.vams
./VERIFICATION/clean
./VERIFICATION/SCRIPTS/run_simulation_voltage_deadband_amplifier
./DUT_VAMS/vdba.vams
Verilog AMS implementation DUT of Voltage deadband amplifier is very simple: the amplifier will “amplify” input voltage signal with the gain of 1, for any voltage except in a “deadband” between 1 -2 V:
// vdba.vams
`include "disciplines.vams"
`timescale 1ns / 1ns
module vdba(in, out);
input in ;
output out ;
electrical in, out ;
parameter real vin_low = 1.0 ;
parameter real vin_high = 2.0 ;
parameter real gain = 1 from (0:inf) ;
analog begin
if (V(in) >= vin_high) begin
V(out) <+ gain* V(in) ;
end
else if (V(in) <= vin_low) begin
V(out) <+ gain* V(in) ;
end
else begin
V(out) <+ 0 ;
end
end
endmodule
Verilog AMS implementation of a simple ( not self-checking ) Voltage deadband amplifier test/testbench of the DUT do a following:
- increments DUTs input voltage every 1 ns for 0.1V until it reaches 5V:
// top_vol_deadb_amp.vams
`include "disciplines.vams"
`timescale 1ns / 1ns
module top_deadb_amp;
electrical vin ;
real d_vin;
electrical vout;
initial begin
d_vin = 0;
end
always begin
#1;
if ( d_vin <= 5 )
d_vin = d_vin + 0.1 ;
else
$finish ;
end
analog begin
V(vin) <+ d_vin ;
end
vdba vdba (
.in ( vin ) ,
.out ( vout )
);
endmodule
To execute the simulation just do this:
- cd <local path>/VERIFICATION
- ./SCRIPTS/run_simulation_voltage_deadband_amplifier
In a waveforms, here is a result of simulation:
- while input is incrementing between 0 and 5V , output is following it except “deadband” in the range of 1-2V when the output is 0V:
© 2011-2019 ASIC Stoic. All rights reserved
