Cadence Virtuoso CMOS Analog Design Basics: an example of adding a schematic for generating a reference current ( e.g. 10uA ) in a new techno ( e.g. TSMC 22nm )

Cadence Virtuoso CMOS Analog Design Basics: an example of adding a schematic for generating a reference current ( e.g. 10uA )  in a new techno ( e.g. TSMC 22nm ) 

Hi,

In the last blog entry: “Cadence Virtuoso CMOS Analog Design Basics: an example of transistor sizing when using the first time new techno ( e.g. TSMC 22nm ) and

we need NMOS transistor in saturation with ID=400uAV” in the final schematic 

I still kept ideal 10uA current source.

In this blog entry I will finish the previous design by adding schematic for generation 10uA current source. The topology chosen here is something called:

“Constant gm bias circuit” or “Beta-multiplier reference circuit”.

Note*: a MOSFET implementation of a Constant gm bias circuit is very well explained by prof. Jacob Baker in his book “CMOS Circuit Design, Layout, and  Simulation” or

in his university lectures available online. 

• Here is a quick explanation of the basic idea of the MOSFET implementation of a Constant gm bias circuit 
  
  
• Let’s start with this schematic:
  
  

Note*: I covered some transistors sizing W and L information ( covered L’s and W’s that might not be

Wmin and Lmin any more in the final schematic ) in order to explain step by step how I got these

 transistor sizes. The same applies for the resistor value R0.

  

Now let’s say I am able to force ( somehow) the same Iref=10uA current through both transistors.

• Obviously in this case width W of transistor M5 and width  W of transistor M4 are not the same so let’s assume : W(of transistor M5)= k*W(of transistor M4)
  
  
• Note* For the moment I am choosing lengths L of both transistors to be the same
  
  

In order to force 10uA  current through M5 ( and M4 ) let’s add a pmos current mirror on the top, designed in such a way to give as the 10uA  current through M5 and M4.

• A friendly reminder: as in previous blog entry these are  TSMC 22nm process RF NMOS and PMOS transistors that I have chosen to use for the schematic :
  
  

• Please tell me if I am wrong but I concluded that need alim of VDD = 2.5V to use this techno/transistors.
  
  

Next I need to  size the four MOSFET transistors ( NMOS: M4, M5 and PMOS: M6, M7 ) and choose a value for resistor R to achieve my goal of having Iref = 10uA.

• As a starting point I have chosen default minimum size:  Lmin, Wmin and NRmin( finger number) for all TSMC 22nm RF NMOS PMOS transistors
  
  
• except M4 that we know has to have its W four times the W of the transistor M5:

In the next step I “sweeped” resistance R while observing ID5 t get ID5=10uA and  found that I need R=28K.

• So here is a final schematic of “Constant gm bias circuit” producing the reference current of  Iref=10uA i
  
  
• mplemented with minimum sizes of TSMC 22nm RF NMOS PMOStransistors and R=28K:

As a last step I will connect this Iref source circuit where I needed it in the schematic of the previous blog entry:

And here is a final schematic with the last adjustment in L of NMOS transistor M1 ( old L=350nm and the new one L=500nm )

to get as close as possible to its desired current of 400uA ( to be precise it is achieved ID1=397uA ).:

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