Cadence Virtuoso CMOS Analog Design Basics: an example of transistor sizing when using the first time new techno ( e.g. TSMC 22nm ) and we need NMOS transistor in saturation with ID=400uAV

Cadence Virtuoso CMOS Analog Design Basics: an example of transistor sizing when using the first time new techno ( e.g. TSMC 22nm ) and we need NMOS transistor in saturation with ID=400uAV

Hi,

I just got into new TSMC 22nm techno  and I wanted to bias one of its NMOS RF transistors using 10uA current source , to get ID=400uA.

This is an TSMC 22nm  RF NMOS and PMOS transistors that I have chosen to use for the task:

Please tell me if I am wrong but I concluded that need alim of VDD = 2.5V to use this techno/transistors.

In a first step  setup a schematic ( like this one bellow)  and after VGS voltage DC sweep ( observing transistor ID current )
I got that, for VDD=2.5V as constant, for VGS=875mV I am getting desired Id approx. 400uA ( or to be exact .403.3uA ).

Note*: for TSMC 22nm  RF NMOS transistor I kept for the moment a default minimum size:  Lmin, Wmin and NRmin( finger number):

Next step is to bias M1 transistor with VGS1=875mV. 

Here is a topology used to get biasing of M1 transistor and as a friendly reminder I assume that I have on my disposal a current of 10uA and I want that M1  ID=400uA.

Note*: I covered some transistors sizing W and L information ( covered L’s and W’s are not Wmin and Lmin any more in the final schematic ! ) in order to explain step by step how I got these  transistor sizes.

 As a first step I did a quick experiment where I put all transistors on their default sizes but in DC simulation  I got M1 ID too high: 1.589mV related to my desired 400uA 

• This is because VGS1 = VDS of  a transistor M0 is to high 1.82V related to desired  VGS1 = 0.872mV

Since this is the transistor equation used for the sizing calculation:

in the next step I tried to increase M0 transistor W in order reduce its VDS=VGS1 and consequently to reduce ID of transistor M1.

Unfortunately even if I used maximum M0 transistor W = 10uA ( still keeping Lmin and NRmin , finger numbers ) 
ID of transistor M1 was better than before but still too high: 1.16mA ( a friendly reminder: the desired value is 400uA )

In the next step I kept maximum M0 transistor W = 10uA but I did a sweep NR( finger number maximum 32 ) and for NR=22 I got the desired current of M23 ID approx. 400uA:

But this “brute force” solution is using too big M0 transistor that is burning a lot of power:, transistor M0 ID0 = 480uA.

Let’s try another approach, I will keep transistor M0 Wmax=10uA ( still keeping Lmin and NRmin)  but I will increase L of PMOS transistor to Lmax=500nm.

• This approach should  increase voltage VDS=VGS of transistor M2 and as result decrease VGS1 and transistor M1 ID current (  a new value of M1 ID current = 757uA while burning ID0 = 111uA of transistor M0 )

 In the last step, to reduce transistor M1 ID1 current from 757uA to desired 400uA, I did a parameter sweep of transistor M1 L ( while observing  M1 ID1 current ) and
for the value transistor M1 L=350nm => transistor M1 ID1 became approx. 400uA ( to be exact: transistor M1 ID1=407.9uA ):

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