ASIC Stoic: Cadence Virtuoso CMOS Analog Design Basics in TSMC 22nm: “Constant gm bias circuit” with start-up and reduced sensitivity to changes in VDD

Cadence Virtuoso CMOS Analog Design Basics in TSMC 22nm: “Constant gm bias circuit” with start-up and reduced sensitivity to changes in VDD

In the previous blog post: “Cadence Virtuoso CMOS Analog Design Basics: a schematic for generating a reference current ( e.g. 10uA ) in a new techno ( e.g. TSMC 22nm )
using “Constant gm bias circuit” with start-up” I didn’t pay attention to what is my circuit sensibility to changes in VDD .

A friendly reminder of the previous blog spot schematic:

A problem: the previous blog spot schematic sensibility to changes in VDD:

One solution to the problem of increased sensitivity of our “Constant gm bias circuit” to changes in VDD is very well described in James Baker book “CMOS

Circuit Design, Layout, and Simulation” and his online available lectures.

The cause of the problem of the large sensitivity to changes in VDD are low output resistance on NMOS transistors M4 and M5 because of “short channel”
technology TSMC 22nm.

As a consequence of the low output resistance there increased sensibility of M4 and M5 current to changes in VDS4 and VDS5 caused by VDD changes.

As a conclusion we need to reduce the variations in the drain-to-source

voltages of the NMOS devices M4 and M5 with changes in VDD and to do this we will:

Disconnect gate drain connection of PMOS transistor M7
Add opamp in negative feedback ( like it is almost always used ) that will keep drain-to-source voltages ( of the NMOS devices M4 and M5 ) always the
same independent of VDD changes

The idea is to use the amplifier to compare the drain voltage of M4 with the drain voltage of M5 and regulate them to be equal:

Now the question is where to connect “+” and where to connect “-” input of opamp ?

By the way It can be proven that Rout of M5 > Rout of M4 .

Here is how the negative feedback operates illustrated on an example:

when gate of M6/M7 goes down ( e.g. because of because of a VDD change .. ), increasing currents ID6 = ID4 and ID7 = ID5 ,
=> this will cause that VDS5 rise more than VDS4 and finally that this rise of VDS5 more than VDS4
=> this will cause that gate voltage of M6/M7 goes up ( and compensate that it went down in the first place ).

=> “+” input of op-amp should be connected to the drain of NMOS transistor M5.

Before I introduce op-amp to the schematic let’s go through an intermediate step and introduce Voltage Control Voltage Source ( vcvs ) from Cadence Virtuoso library
analogLib as a good approximation of opamp especially if we setup in vcvs a Voltage Gain parameter ( A ) to some high value ( e.g. A = 10000 or 20*log 10000 = 80db )

Here we can see an improvement in much less sensitivity of Iref = 10uA on VDD changes.

Note*: Just a friendly reminder so far we did experiments assuming Voltage Gain = 10 000 ( 80 dB ) but in reality a single stage simple op amp that we are going to use
here will have more Voltage Gain = 50 ( 20*log (50) approx. 34dB.