Cadence Virtuoso CMOS Analog Design Basics in TSMC 22nm: a simple op-amp design with a High Swing Cascode current mirror- Part 2

Introduction

In the previous blog post “Cadence Virtuoso CMOS Analog Design Basics in TSMC 22nm: a simple op-amp design with a High Swing Cascode current mirror” we fished design of a High Swing Cascode current mirror.

In this blog post we will finally design a simple opamp that will reuse our High Swing Cascode current mirror.

A design of a simple opamp is very well explained by  Hafeez KT, in his youtube lecture available online and here is a basic topology:

A summary of specification points that will be achieved in this opamp design:

• our op amp has to drive capacitive load of C1 = 10pf with a 
• Slew Ratio ( SR ) = 2V/second
• Input Common Mode Range ( negative, minimum ):  ICMR- = 1.2V
• Voltage on differential pair inputs should never be less than  1.2V
• Input Common Mode Range ( positive, maximum  ): ICMR+ = 3.0V 
• Voltage on differential pair inputs should never  not exceed 3.0V
• Gain Bandwidth product ( GB ) > 3MHz)

Note* : L=1u for all transistors.

Calculation the value of current to be provided by M5 

A friendly reminder that our op amp has to have:

• drive capacitive load of C1 = 10pf with a 
• Slew Ratio ( SR ) = 2V/second

=>SR is rate of changing voltage across load capacitance C1

Q = C1 * V

dQ/dt = C1*dV/dt

I capacitance = C1*dV/dt

C1 is charging when differential pair branch M1/M3 is conducting ( consequently branch M4/M2 is not conducting ) with all the current I.

C1 is discharging when differential pair branch M4/M2 is conducting ( consequently branch M1/M3 is not conducting ) with all the current I.

Conclusion I of capacitance = I is:

=> I = C1*dV/dt

=> I = C1*SR

=> I = 10pF*2V/ u second = 20uA

=> I0 or ID5 = 20uA

Estimating ( by simulation )  p*Cox and n*Cox

for TSMC 22nm process PMOS and NMOS

transistor used

The technology that we are using here ( TSMC 22nm ) is new to me and I am

using pmos transistor pch_25od33_mac ( for M3/M4, pmos active load )  and I

don’t know its    

In general to calculate  W/L for M3/M4 we will use formula:

Then I setup a following simulation to find ( approx.) :

• VDS = 3.3V
• Idc = 10uA
• W=10um
•  L=1u

The DC simulation showed Vthp=603.8mV and Vgs=Vds=763.4mV

=> = 2*10uA/( ( 10um/1um) * (763.4mV - 603.8mV)^^2 ) 

=> = 7.85*( 10 ^^ -5 )

       Vth_p    = 603.8mV

Also I am using nmos transistor nch_25od33_mac ( for M1/M2, nmos differential pair  ) and here also I don’t know its n*Cox

Then I setup following simulation to find ( approx.) n*Cox

• Idc = 10uA
• W=10um
•  L=1u

The DC simulation showed Vthn=672.2mV and Vgs=Vds=727.7mV

=> n*Cox= 2*10uA/( ( 10um/1um) * (727.7mV - 672.2mV)^^2 ) 

=> n*Cox= 649.2*( 10 ^^ -6 )

     Vth_n = 672mV 

Calculation of  W/L for M3/M4 ( pmos active load ) 

A friendly reminder of a points in specification:

• Input Common Mode Range ( positive, maximum  ) , ICMR+ = 3.0V
• Voltage on differential pair inputs should never  not exceed 3.0V

For calculation of  W/L for M3/M4 ( pmos active load ) let’s focus on highlighted transistors M1/M2:

for transistor M0 to be in saturation VDS3 > VGS3 -Vth_p and ID1=ID3 = 10uA

if Vx = VD1 = VD3 and VDS1 > VGS1 - Vth_n => VD1 > VG1 - Vth_n

=> Vx > Vin_p -Vth_n

A friendly reminder: Vth_p    = 603.8mV and Vth_n = 672mV 

Maximum voltage on Vin_p = 3.0 V ( this is based on  ICMR+ = 3.0V ) and for Vin_p = 3.30V Vth-n=0.672

=>  Vx > 3.0V - 0.672 V = 2.328 V so we can adopt Vx  = VD1= VD0= 2.5V 

Since M0 is in saturation too, and VS0 = VDD :

=> VSD3 = VS3 -VD3 = VDD - 2.5 =3.3V -2.5  = 0.8V 

=> VDS0 =VGS0 = 0.8V 

A friendly reminder: = 7.85*( 10 ^^ -5 )

=> W/L( PMOS M3) = 2*10uA/(79u*(0.8 -  0.604 )^^2 ) 

W/L( PMOS M3) =6.58 approx. 7

Calculation of  W/L for M1/M2 ( nmos diff. pair ) 

For calculation of  W/L for M1/M2 ( nmos differential pair ) let’s focus on highlighted transistors M4/M2:

A friendly reminder of a couple specification points of our opamp::  

• Gain Bandwidth product ( GB ) > 3MHz
•  opamp is driving a capacitive load of 10pF

We will use formula GB=  DC gain * (first) pole

It can be proven that: 

• 
• First pole:

=>

gm2= 3MHz*2*3.14*10pF= 188u

And because M2= M1 => gm2 = gm1

Finally to calculate M1,2 W/L we will use a formula gm=f(ID, W/L):

A friendly reminder:

•  Vth_p    = 603.8mV and Vth_n = 672mV 
• = 7.85*( 10 ^^ -5 )
• n*Cox= 649.2*( 10 ^^ -6 )

=>  W/L ( for NMOS M1 and M2 ) = 2.74 approx. 3  

Fully transistor sized schematic ( but no current source implemented  yet )

Finally our ( fully sized transistors )  schematic ( after DC simulation with annotated DC operating points ) including:

• Vdd = 3.3V
• Vin = 1V

But did we achieve a point of the spec Gain Bandwidth product ( GB ) > 3MHz ?

A friendly reminder that Gain Bandwidth product is a frequency where 20log(output voltage/input voltage)=0dB and in our case Gain Bandwidth product is only 1.48MHz:

The lower than expected GB  is because a low value for gm of transistors

M1/M2 ( nmos differential pair ): gm1/2= 93.6u and to achieve

GB > 3MHz we calculated that gm1,2 should be gm1/2= 188u.

And to increase gm1,2 we need to further increase W1,2 to  W1,2=24u

to achieve gm1,2=188u :

Another useful check is to, in DC simulation,  “sweep” Vin from 0V to

3.3V ( VDD ) and to check that for  the range of valid Vin voltages (

ICMR- = 1.2V, ICMR+ = 3.0V )  all four transistors are in saturation:

Fully transistor sized schematic

Now we are replacing the ideal current source with High Swing Cascode

current mirror ( designed in the previous blog entry ):

Again the  useful check to “sweep” Vin from 0V to 3.3V ( VDD ) in DC

simulation, and to verify  that for the range of valid Vin voltages ( ICMR-

= 1.2V, ICMR+ = 3.0V ) all four transistors of opamp core are in

saturation:

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