Verilog RTL verification
Python, CocoTB infrastructure (and it’s testing) for an UART verification; the infrastructure testing is done without a need for a presence of an actual UART DUT design
A simple Python, CocoTB verification interface for UART verification, again independently tested using again Python/CocoTB with no full UART DUT design necessary
Exploring Python and CocoTB Infrastructure for Testing Without an Actual DUT Design
In this blog post, we will explore a simple Python and CocoTB infrastructure for UART verification. The aim is to test the functionality of the UART interface without the need for an actual UART Design Under Test (DUT) implementation. The Python code utilizes CocoTB, a Python-based framework for verification and testing of digital designs.
In one of the previous blog posts dedicated to CoCoTB and titled "CoCoTB based verification: A small example(https://asicstoic.blogspot.com/2023/06/cocotb-based-verification-small-example.html#comment-form) there is an introduction to CoCoTB (Coroutine-based Co-simulation Test Bench), an open-source Python library used for hardware design verification and testing. The post provides a small example of a CoCoTB testbench/test implemented using the icarus simulator and explains CoCoTB’s key concepts and features.In the last post there is also an explanation of the directory structure and Makefile to facilitate running the simulation . All of this is not going to be repeated in this blog post.
In this blog post files involved are:
A dummy DUT UART module (test_uart.v)
One minor inconvenience with CocoTB is the apparent requirement of having a simulator to run tests. However, in cases where we don't have any DUT/UART RTL Verilog code, it becomes necessary to create a straightforward DUT/UART Verilog module, for example with just a single data signal that we can easily connect to.
Python, CocoTB infrastructure and its testing (test_uart.py).
Here is a source code of the blog post files
test_uart.v (the DUT)
test_uart.py
Let's start by examining the Python code that represents the UART verification infrastructure and the infrastructure testing.
A waveform detail of the verification run
Simulation log file
rm -rf sim_build
make sim MODULE=test_uart TOPLEVEL=test_uart
make[1]: Entering directory '<user path>/cocotbext_uart'
rm -f results.xml
make -f Makefile results.xml
make[2]: Entering directory '<user path>/cocotbext_uart'
mkdir -p sim_build
/usr/bin/iverilog -o sim_build/sim.vvp -D COCOTB_SIM=1 -s test_uart -f sim_build/cmds.f -g2012 <user path>cocotbext_uart/test_uart.v
rm -f results.xml
MODULE=test_uart TESTCASE= TOPLEVEL=test_uart TOPLEVEL_LANG=verilog \
/usr/bin/vvp -M /home/tilic/.pyenv/versions/3.11.3/lib/python3.11/site-packages/cocotb/libs -m libcocotbvpi_icarus sim_build/sim.vvp
-.--ns INFO gpi ..mbed/gpi_embed.cpp:76 in set_program_name_in_venv Did not detect Python virtual environment. Using system-wide Python interpreter
-.--ns INFO gpi ../gpi/GpiCommon.cpp:101 in gpi_print_registered_impl VPI registered
0.00ns INFO cocotb Running on Icarus Verilog version 11.0 (stable)
0.00ns INFO cocotb Running tests with cocotb v1.8.0 from /home/tilic/.pyenv/versions/3.11.3/lib/python3.11/site-packages/cocotb
0.00ns INFO cocotb Seeding Python random module with 1688562410
0.00ns INFO cocotb.regression pytest not found, install it to enable better AssertionError messages
0.00ns INFO cocotb.regression Found test test_uart.run_test_001
0.00ns INFO cocotb.regression running run_test_001 (1/1)
Automatically generated test
<user path>/cocotbext_uart/test_uart.py:51: DeprecationWarning: cocotb.fork has been deprecated in favor of cocotb.start_soon and cocotb.start.
In most cases you can simply substitute cocotb.fork with cocotb.start_soon.
For more information about when you would want to use cocotb.start see the docs,
https://docs.cocotb.org/en/latest/coroutines.html#concurrent-execution
cocotb.fork(self._run())
<user path>/cocotbext_uart/test_uart.py:156: DeprecationWarning: cocotb.fork has been deprecated in favor of cocotb.start_soon and cocotb.start.
In most cases you can simply substitute cocotb.fork with cocotb.start_soon.
For more information about when you would want to use cocotb.start see the docs,
https://docs.cocotb.org/en/latest/coroutines.html#concurrent-execution
cocotb.fork(self._run())
<user path>/cocotbext_uart/test_uart.py:103: DeprecationWarning: Setting values on handles using the ``handle <= value`` syntax is deprecated. Instead use the ``handle.value = value`` syntax
self.data <= 0
<user path>/cocotbext_uart/test_uart.py:118: DeprecationWarning: Setting values on handles using the ``handle <= value`` syntax is deprecated. Instead use the ``handle.value = value`` syntax
self.data <= bit
<user path>/cocotbext_uart/test_uart.py:123: DeprecationWarning: Setting values on handles using the ``handle <= value`` syntax is deprecated. Instead use the ``handle.value = value`` syntax
self.data <= 1
Write bit 0: 0
Read bit 0: 0
Write bit 1: 1
Read bit 1: 1
Write bit 2: 0
Read bit 2: 0
Write bit 3: 1
Read bit 3: 1
Write bit 4: 0
Read bit 4: 0
Write bit 5: 1
Read bit 5: 1
Write bit 6: 0
Read bit 6: 0
Write bit 7: 1
Read bit 7: 1
Write bit 0: 1
Read bit 0: 1
Write bit 1: 1
Read bit 1: 1
Write bit 2: 0
Read bit 2: 0
Write bit 3: 1
Read bit 3: 1
Write bit 4: 1
Read bit 4: 1
Write bit 5: 1
Read bit 5: 1
Write bit 6: 0
Read bit 6: 0
Write bit 7: 1
Read bit 7: 1
Write bit 0: 0
Read bit 0: 0
Write bit 1: 0
Read bit 1: 0
Write bit 2: 1
Read bit 2: 1
Write bit 3: 1
Read bit 3: 1
Write bit 4: 0
Read bit 4: 0
Write bit 5: 0
Read bit 5: 0
Write bit 6: 1
Read bit 6: 1
Write bit 7: 1
Read bit 7: 1
Write bit 0: 1
Read bit 0: 1
Write bit 1: 0
Read bit 1: 0
Write bit 2: 1
Read bit 2: 1
Write bit 3: 1
Read bit 3: 1
Write bit 4: 1
Read bit 4: 1
Write bit 5: 0
Read bit 5: 0
Write bit 6: 1
Read bit 6: 1
Write bit 7: 1
Read bit 7: 1
User received data:
bytearray(b'\xaa\xbb\xcc\xdd')
4010391.00ns INFO cocotb.regression run_test_001 passed
4010391.00ns INFO cocotb.regression **************************************************************************************
** TEST STATUS SIM TIME (ns) REAL TIME (s) RATIO (ns/s) **
**************************************************************************************
** test_uart.run_test_001 PASS 4010391.00 0.01 453721010.36 **
**************************************************************************************
** TESTS=1 PASS=1 FAIL=0 SKIP=0 4010391.00 0.10 40232772.17 **
**************************************************************************************
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