SystemVerilog RTL verification

UVM like (non-UVM) verification environment verifying a DUT with handshake controlled input and output

A case of the non-UVM (but UVM-like) Verification Environment of a DUT that features a handshake-controlled input and output data transfers

Introduction 2

Verification environment architecture 2

Individual functioning (and interconnection between them), of all verification architecture elements 2

DUT 5

Interface 7

testbench.sv ( top testbench module ) 7

Transaction Class 9

Generator Class 10

Driver Class 11

Environment Class 15

Test Program 17

Monitor Class 18

Scoreboard Class 19

Verification waveforms 20

Simulation/Verification log 21

Introduction

The Universal Verification Methodology (UVM) has long been the go-to framework for system verification, providing a robust and standardized approach. In this blog post we delve into a System VerilogUVM-like verification infrastructure , an UVM alternative verification infrastructure that offers similar benefits while diverging from the UVM framework of dedicated UVM specific verification code.

Verification environment architecture

Individual functioning (and interconnection between them), of all verification architecture elements

Here is how all System Verilog verification elements are connected in this architecture and an explanation of their individual functioning.

testbench.sv (architecture block diagram: TestBench_Top)

Generatest POR ( lines 24-29) and system clock ( lines: 21-22)
Instantiates and connects following parts together: random_test.sv ( the verification test: lines: 10 and 36 ), DUT RTL( lines: 39-49) and interface.sv (DUT’s interface: lines: 6 and 33)
Count clock ticks to finish simulation after a predetermined number of clock ticks is reached (lines: 58-67).
Capture waveforms data ( vcd file,lines: 52-55 )

random_test.sv (architecture block diagram: test)

System Verilog test in the present System Verilog testbench verification architecture. Only one test can be executes at the time in the architecture.
It is implemented using SystemVerilog “program” that interface with the testbench.sv/DUT via interface.sv.
Declares and creates environment.sv and then executes environments main task “run”

environment.sv (architecture block diagram: env)

declare interface and gets the interface from the test
declare and create two mailboxes (to pack transactions in them):

gen2driver ( transactions passed from generator to driver)
mon2scb ( transactions passed from monitor to scoreboard)

declare and create:

generator.sv

Input argument: gen2driver

driver.sv

Input arguments: gen2driver and interface

monitor.sv

Input arguments: mon2scb and interface

scoreboard.sv

Input argument: mon2scb

main verification test task: “run” executes the System Verilog verification test in the present architecture

end of “run” task execution is the end of the verification test.
“run” activity can be divided and controlled in three methods:

pre_test() - Method to call Initialization. i.e, reset method.

e.g. The reset task is defined inside driver ( The reset task is driver class “method” )

test()

Execute in parallel the main task (“main”) in all four main verification architecture components: generator, driver, monitor and scoreboard.

post_test() - Method to wait for the completion of the verification test

First it waits end that all transactions are generated. The number of the transactions is previously determined, in other words it is programmable.
Finally it waits until the scoreboard finishes checking all results stored in transactions.

generator.sv (architecture block diagram: generator)

declares mailbox handle and get the environments mailbox: gen2driver through constructor
generates predetermined number of transactions for the driver and stores the generated transactions into environments mailbox: gen2driver
Indicates ( by triggering an event) the end of packets generation

driver.sv (architecture block diagram: driver)

declares mailbox handle and gets the environments mailbox: gen2driver through constructor
declares interface handle and gets the interface ( from the test: random_test.sv ) through constructor
The reset task is defined inside driver ( The reset task is driver class “method” )

The reset task is later used by the environment in its main verification test task: “run” in sub-task: pre_test() a method to call Initialization (i.e, reset method).

The main driver task: “main”

provides two loops in parallel ( using fork …. join): one loop is interfacing to provide input data to DUT as a producer and the other is interfacing to do output data take over from DUT, as a consumer.

“producer” loop first waits a randomized number of clock cycles ( between 1 and 20) before it signals to DUT that there is a random input data( from the mailbox: gen2driv) available. This will take place only if output data ( if any available ) already left DUT or there is no previous input data not yet accepted by DUT.
“producer” loop will provide to DUT, a predetermined number of iterations, input data each waiting for a previous DUT output data to be “consumed” first.

when a random input data is accepted by DUT, the driver sets up a flag that that “transaction is available” necessary for the “consumer” loop to execute. The “consumer” loop will clear the flag “transaction is available” every time a DUT output data is “consumed”.

when DUT signals that an output data is available, the “consumer” loop first waits a randomized number of clock cycles ( between 1 and 20) before it “consumes” the data . After this the “consumer” loop will clear the flag “transaction is available” to signal the “producer” loop to make next randomized input data available to DUT.

monitor.sv (architecture block diagram: monitor)

declares mailbox handle and gets the environments mailbox: mon2scb through constructor
declares interface handle and gets the interface ( from the test: random_test.sv ) through constructor
provides two “waits” in parallel ( using fork …. join): one “wait” is waiting until DUT accepts input data and the other “wait” is waiting until DUT’s output data is “consumed”. After the both “waits” are individually executed, after the first “wait” a data input is saved in a transaction and in the same manner after the second “wait” the output data is sampled and saved in the same transaction. Every clock cycle the transaction is “pushed” in the mailbox mon2scb, later to be used by scoreboard in a verification self-checking.

scoreboard.sv (architecture block diagram: scoreboard)

declares mailbox handle and gets the environments mailbox: mon2scb through constructor
For every transaction from mailbox mon2scb, the scoreboards checks that input data is the same as output data because the functionality of our simple DUT was just that: transfer the same data in and out of the DUT using the handshake control on both ends: input and output.

DUT

DUT input and output data exchange controls using handshake interfaces is based on Producer/Consumer exchange of data. The same DUT and the handshake mechanism were already described in one of the previous blog posts: https://asicstoic.blogspot.com/2023/06/verilog-rtl-verification-cocotb-based.html

module SimpleDUT_hs (
input CLK,
input RST_N,

input en_din_i,
output logic rdy_din_o,
input [3:0] din_i,

input en_dout_i,
output logic rdy_dout_o,
output logic[3:0] dout_o
);

// Define the states using localparam
localparam START_ST = 1'b0;
localparam WR_ST = 1'b1;

logic next_rdy_dout;

logic[3:0] next_dout ;

logic state, next_state ;

always @(posedge CLK or negedge RST_N) begin
if (!RST_N) begin
state <= START_ST;
rdy_dout_o <= 1'b0 ;
dout_o <= 4'd0 ;
end else begin
state <= next_state ;
rdy_dout_o <= next_rdy_dout ;
dout_o <= next_dout ;
end
end

always @(*) begin
next_state = state ;
next_rdy_dout = rdy_dout_o;
next_dout = dout_o;

rdy_din_o = 1'b0;
case(state)
////////////////////////////
START_ST: begin
if(en_din_i) begin
next_dout = din_i;
rdy_din_o = 1'b1;

next_rdy_dout = 1'b1;

next_state = WR_ST;
end
end

///////////////////////////
WR_ST: begin
case({en_din_i, en_dout_i})
2'b00, 2'b10:
next_state = state ;
2'b01: begin
next_rdy_dout = 1'b0;
next_state = START_ST;
end
2'b11: begin
next_dout = din_i;
rdy_din_o = 1'b1;
end
endcase

end
endcase
end

endmodule

Interface

The name of the file is: interface.sv .

interface intf(input logic CLK,RST_N);

//declaring the signals
logic en_din_i;
logic rdy_din_o;
logic [3:0] din_i;

logic en_dout_i;
logic rdy_dout_o;
logic [3:0] dout_o ;

endinterface

testbench.sv ( top testbench module )

1 //tbench_top or testbench top: this is the top most file, in which DUT(Design Under Test) and Verification environment are connected.
2 //-------------------------------------------------------------------------
3
4
5 //including interface and testcase files
6 `include "interface.sv"
7
8 //-------------------------[NOTE]---------------------------------
9 //Particular testcase can be run by uncommenting, and commenting the rest
10 `include "random_test.sv"
11 //----------------------------------------------------------------
12
13 module tbench_top;
14
15 //clock and reset signal declaration
16 bit CLK;
17 bit RST_N;
18
19 integer clk_counter = 0; // Counter to keep track of clock cycles
20
21 //clock generation
22 always #5 CLK = ~CLK;
23
24 //reset Generation
25 initial begin
26 RST_N = 1;
27 #1 RST_N =0;
28 #1 RST_N =1;
29 end
30
31
32 //creating instance of interface, in order to connect DUT and testcase
33 intf i_intf(CLK,RST_N);
34
35 //Testcase instance, interface handle is passed to test as an argument
36 test t1(i_intf);
37
38 //DUT instance, interface signals are connected to the DUT ports
39 SimpleDUT_hs DUT (
40 .CLK (i_intf.CLK),
41 .RST_N (i_intf.RST_N),
42
43 .en_din_i (i_intf.en_din_i),
44 .rdy_din_o(i_intf.rdy_din_o),
45 .din_i (i_intf.din_i),
46
47 .en_dout_i (i_intf.en_dout_i),
48 .rdy_dout_o(i_intf.rdy_dout_o),
49 .dout_o (i_intf.dout_o) );
50
51
52 //enabling the wave dump
53 initial begin
54 $dumpfile("dump.vcd"); $dumpvars;
55 end
56
57
58 always @(posedge CLK) begin
59 // Increment the clock counter
60 clk_counter = clk_counter + 1;
61
62 // Check if the counter reaches 500
63 if (clk_counter == 500) begin
64 $display("Simulation stopped after 500 clock cycles");
65 $finish; // Stop the simulation
66 end
67 end
68
69 endmodule

Transaction Class

The name of the file is: transaction.sv .

class transaction;

// declaring the transaction items
// Instantiation of logic/wires/registers,same as used in interface, go here
// so in other words: straight copy from interface

logic en_din_i;
logic rdy_din_o;

// We are going to use this to generate random values of DUT input port data on one hand and to store the output data result and all handshake signals on the other hand.
rand logic [3:0] din_i;

logic en_dout_i;
logic rdy_dout_o;
logic [3:0] dout_o;

// Adding display() method to display Transaction properties.
function void display(string name);
$display("-------------------------");
$display("- %s ",name);
$display("-------------------------");
$display("- en_din_i = %0d, rdy_din_o = %0d, din_i = %0d", en_din_i, rdy_din_o, din_i );
$display("- en_dout_i = %0d, rdy_dout_o = %0d, dout_o = %0d", en_dout_i,rdy_dout_o, dout_o);
$display("-------------------------");
endfunction
endclass

Generator Class

Generating the randomized DUT input data, a part of the transaction class. The produced data is used by the driver class as DUT input data stimulus.

The name of the file is: generator.sv .

class generator;

//declaring transaction class handle
rand transaction trans;

//repeat count, to specify number of items to generate
int repeat_count;

//mailbox, to generate and send the randomized packet( DUT data input) to driver
mailbox gen2driv;

//event, to indicate the end of transaction generation
event ended;

//constructor
function new(mailbox gen2driv);
//getting the mailbox handle from env, in order to share the transaction packet between the generator and driver. The same mailbox is shared between both.
this.gen2driv = gen2driv;
endfunction

//main task, generates(create and randomizes) the repeat_count number of transaction packets and puts them into mailbox
task main();
repeat(repeat_count) begin
trans = new();
// 'Randomize' the transaction class
if( !trans.randomize() ) $fatal("Gen:: trans randomization failed");
trans.display("[ Generator ]");
gen2driv.put(trans);
end
-> ended; //triggering/indicatings the end of packets generation
endtask

endclass

Driver Class

Receive the stimulus (randomized DUT input data, one of transaction class values) generated from the generator and drive it to DUT using randomized DUT input handshake control signal. Also using randomized DUT output handshake control signal causes DUT output data “consumption”.

The name of the file is: driver.sv

1 //gets the packet from generator and drive the transaction packet items into interface (interface is connected to DUT, so the items driven into interface signal will get driven in to DUT)
2 class driver;
3
4 //used to count the number of transactions
5 int no_transactions;
6
7 //creating/declaring virtual interface handle
8 virtual intf vif;
9
10 //creating/declaring mailbox handle
11 mailbox gen2driv;
12
13 transaction trans;
14
15 //constructor
16 function new(virtual intf vif,mailbox gen2driv);
17 //getting the interface handle through a constructor
18 this.vif = vif;
19 //getting the mailbox handles from environment, through a constructor
20 this.gen2driv = gen2driv;
21 endfunction
22
23 //Reset task, Reset the Interface signals to default/initial values
24 task reset;
25 wait(!vif.RST_N);
26 $display("[ DRIVER ] ----- Reset Started -----");
27 vif.en_din_i <= 0;
28 vif.din_i <= 0;
29 vif.en_dout_i <= 0;
30 wait(vif.RST_N);
31 $display("[ DRIVER ] ----- Reset Ended -----");
32 endtask
33
34 //drivers the transaction items to interface signals
35 task main;
36 integer j, i;
37 integer num_iterations = $urandom_range(1, 21);
38 integer num_iterations2 = $urandom_range(1, 21);
39 logic trans_available = 0; // Flag to indicate if trans is available
40
41 // two loops in parallel: data to/from DUT
42 fork
43 // Loop of input handshake control/data from verification environment to DUT
44 forever begin
45 num_iterations = $urandom_range(1, 21);
46 @(posedge vif.CLK);
47 if( vif.rdy_dout_o && !vif.en_dout_i )
48 vif.en_din_i <= 0;
49 else
50 if( !vif.en_din_i ||
51 (vif.en_din_i && vif.rdy_din_o)) begin
52 // get a new transaction if previous input data is already accepted by DUT
53 // or there was no input data to begin with waiting to be accepted by DUT
54 gen2driv.get(trans);
55 // wait random number of clock cycles ( between 0 and 20 ) to start input data handshake request
56 for (j = 0; j < num_iterations; j++) begin
57 @(posedge vif.CLK);
58 end
59
60 // if previous data is not either accepted yet by DUT, or DUT didn't output yet
61 // the previous data: no input handshake request
62 if(
63 vif.en_din_i ||
64 ( vif.rdy_dout_o && !vif.en_dout_i )
65 )
66 vif.en_din_i <= 0;
67 else begin
68 //if there is no previous data waiting to be accepted by DUT, and DUT don't have any data to output: make a new input data handshake request
69 vif.din_i <= trans.din_i;
70 vif.en_din_i <= 1;
71 end
72 // store in transaction class: state of input handshake signals
73 // although at the moment they are not used in monitor/scoreboard and it is used only in “display” for debugging/following data flow.
74 trans.en_din_i = 1;
75 trans.rdy_din_o = vif.rdy_din_o;
76
77 // output handshake is going to get initiated only if there
78 // data already accepted on DUT input ( in other words the “transaction” is available.
79 trans_available = 1; // Set the flag to indicate trans is available
80
81 trans.display("[ Driver ]");
82 end
83
84 end
85
86 // Loop of output handshake control/data from DUT to verification environment
87 forever begin
88 num_iterations2 = $urandom_range(1, 21);
89 @(posedge vif.CLK);
90 if(vif.rdy_dout_o && trans_available) begin
91 // if there is DUT output data available, wait
92 // a random number of clock cycles ( between 0 and 20)
93 // to approve DUT output handshake and final output of DUT data from
94 // DUT
95 for (i = 0; i < num_iterations2; i++) begin
96 @(posedge vif.CLK);
97 end
98 vif.en_dout_i <= 1;
99
100 // when data is handshake approved to leave DUT output,
101 // the output data is saved in transaction although it is not used currently

102 trans.dout_o = vif.dout_o;
103
104 // Also store in transaction class: state of input handshake signals
105 // although at the moment they are not used in monitor/scoreboard
106 trans.rdy_dout_o = vif.rdy_dout_o;
107 trans.en_dout_i = vif.en_dout_i;
108
109 // Next DUT input data handshake is going to be initiated only if // previous DUT output data has already left DUT.
110 trans_available = 0; // Reset the flag to indicate trans is no longer available
111 end else begin
112 // if there is no DUT output data available,
113 // reset output data handshake signal
114 vif.en_dout_i <= 0;
115 end
116 end
117
118 join
119
120 endtask
121
122 endclass

Environment Class

Environment is a container class containing Mailbox, Generator, Driver, Monitor and Scoreboard. For each of them, declare the handles and create them individually in the Construct Method.

The name of the file is: environment.sv .

`include "transaction.sv"
`include "generator.sv"
`include "driver.sv"
`include "monitor.sv"
`include "scoreboard.sv"
class environment;

//generator and driver instance
generator gen;
driver driv;
monitor mon;
scoreboard scb;

//mailbox handle's
mailbox gen2driv;
mailbox mon2scb;

//virtual interface
virtual intf vif;

//constructor
function new(virtual intf vif);
//get the interface from test
this.vif = vif;

//creating the mailbox (Same handle will be shared across generator and driver)
gen2driv = new();
mon2scb = new();

//creating generator and driver
gen = new(gen2driv);
driv = new(vif,gen2driv);
mon = new(vif,mon2scb);
scb = new(mon2scb);
endfunction

// Method to call Initialization. i.e, reset method.
task pre_test();
driv.reset();
endtask

// Method to call Stimulus Generation, Stimulus Driving, Data Results monitoring and Scoreboard Results Self-checking
task test();
fork
gen.main();
driv.main();
mon.main();
scb.main();
join_any
endtask

task post_test();
wait(gen.ended.triggered);
wait(gen.repeat_count == driv.no_transactions); //Optional
wait(gen.repeat_count == scb.no_transactions);
endtask

//run task
task run;
// Generator and Driver activity can be divided and controlled in three methods.
// pre_test() - Method to call Initialization. i.e, reset method.
// test() - Method to call Stimulus Generation and Stimulus Driving.
// post_test() - Method to wait for the completion of generation and driving.
pre_test();
test();
post_test();
$finish;
endtask

endclass

Test Program

In Verilog there is a concept of only one design entity and that is: module ( used for both design and testbench ):

to have clear separation between testbench and design, SystemVerilog introduces “program”, which contains a full environment for testbench.

Test code is written with the program block. The test is responsible for creating the environment and configuring the testbench i.e, setting a number of transactions to be generated.

The name of the file is: random_test.sv.

`include "environment.sv"
program test(intf i_intf);

//declaring environment instance
environment env;

initial begin
//creating environment
env = new(i_intf);

//setting the repeat count of generator as 100, means to generate 100 packets
env.gen.repeat_count = 100;

//calling run of env, it interns calls generator and driver main tasks.
env.run();
end
endprogram

Monitor Class

1 //Samples the interface signals, captures into the transaction packet and sends the packet to the scoreboard.
2
3 class monitor;
4
5 //creating virtual interface handle
6 virtual intf vif;
7
8 //creating mailbox handle
9 mailbox mon2scb;
10
11 //constructor
12 function new(virtual intf vif,mailbox mon2scb);
13 //getting the interface
14 this.vif = vif;
15 //getting the mailbox handles from environment
16 this.mon2scb = mon2scb;
17 endfunction
18
19 //Samples the interface signal and send the sample packet to scoreboard
20 task main;
21 forever begin
22 transaction trans;
23 trans = new();
24 @(negedge vif.CLK);
25 fork
26 begin
27 wait(vif.rdy_dout_o && vif.en_dout_i );
28 trans.dout_o = vif.dout_o;
29 end
30
31 begin
32 wait(vif.en_din_i && vif.rdy_din_o );
33 trans.din_i = vif.din_i;
34 end
35 join
36
37 @( negedge vif.CLK);
38 trans.en_din_i = vif.en_din_i;
39 trans.rdy_din_o = vif.rdy_din_o;
40 trans.en_dout_i = vif.en_dout_i;
41 trans.rdy_dout_o = vif.rdy_dout_o;
42 mon2scb.put(trans);
43 trans.display("[ Monitor ]");
44 end
45 endtask
46
47 endclass

Scoreboard Class

Scoreboard receives the sampled packet from the monitor and compares it with the expected result so an error will be reported if the comparison results in a mismatch.

1 //gets the packet from monitor, Generated the expected result and compares with the //actual result received from Monitor
2
3
4 class scoreboard;
5
6 //creating mailbox handle
7 mailbox mon2scb;
8
9 //used to count the number of transactions
10 int no_transactions;
11
12 //constructor
13 function new(mailbox mon2scb);
14 //getting the mailbox handles from environment
15 this.mon2scb = mon2scb;
16 endfunction
17
18 //Compares the Actual result with the expected result
19 task main;
20 transaction trans;
21 forever begin
22 mon2scb.get(trans);
23 if(trans.din_i == trans.dout_o)
24 $display("Result is as Expected");
25 else
26 $error("Wrong Result.\n\tExpeced: %0d Actual: %0d",trans.din_i,trans.dout_o);
27
28 no_transactions++;
29 trans.display("[ Scoreboard ]");
30 end
31 endtask
32
33 endclass

Verification waveforms

Simulation/Verification log

[2023-07-17 13:41:39 UTC] vcs -licqueue '-timescale=1ns/1ns' '+vcs+flush+all' '+warn=all' '-sverilog' design.sv testbench.sv && ./simv +vcs+lic+wait

Warning-[LINX_KRNL] Unsupported Linux kernel

Linux kernel '5.4.0-152-generic' is not supported.

Supported versions are 2.4* or 2.6*.

Chronologic VCS (TM)

Version S-2021.09 -- Mon Jul 17 09:41:40 2023

Parsing design file 'design.sv'

Parsing design file 'testbench.sv'

Parsing included file 'interface.sv'.

Back to file 'testbench.sv'.

Parsing included file 'random_test.sv'.

Parsing included file 'environment.sv'.

Parsing included file 'transaction.sv'.

Back to file 'environment.sv'.

Parsing included file 'generator.sv'.

Back to file 'environment.sv'.

Parsing included file 'driver.sv'.

Back to file 'environment.sv'.

Parsing included file 'monitor.sv'.

Back to file 'environment.sv'.

Parsing included file 'scoreboard.sv'.

Back to file 'environment.sv'.

Back to file 'random_test.sv'.

Back to file 'testbench.sv'.

Top Level Modules:

tbench_top

TimeScale is 1 ns / 1 ns

CPU time: .327 seconds to compile + .398 seconds to elab + .217 seconds to link

Contains Synopsys proprietary information.

Compiler version S-2021.09; Runtime version S-2021.09; Jul 17 09:41 2023

[ DRIVER ] ----- Reset Started -----

[ DRIVER ] ----- Reset Ended -----

-------------------------

- [ Generator ]

-------------------------

- en_din_i = x, rdy_din_o = x, din_i = 13

- en_dout_i = x, rdy_dout_o = x, dout_o = x

-------------------------

- [ Generator ]

-------------------------

- en_din_i = x, rdy_din_o = x, din_i = 6

- en_dout_i = x, rdy_dout_o = x, dout_o = x

-------------------------

- [ Generator ]

-------------------------

- en_din_i = x, rdy_din_o = x, din_i = 15

- en_dout_i = x, rdy_dout_o = x, dout_o = x

-------------------------

- [ Generator ]

-------------------------

- en_din_i = x, rdy_din_o = x, din_i = 15

- en_dout_i = x, rdy_dout_o = x, dout_o = x

-------------------------

- [ Generator ]

-------------------------

- en_din_i = x, rdy_din_o = x, din_i = 7

- en_dout_i = x, rdy_dout_o = x, dout_o = x

-------------------------

- [ Generator ]

-------------------------

- en_din_i = x, rdy_din_o = x, din_i = 15

- en_dout_i = x, rdy_dout_o = x, dout_o = x

-------------------------

- [ Generator ]

-------------------------

- en_din_i = x, rdy_din_o = x, din_i = 4

- en_dout_i = x, rdy_dout_o = x, dout_o = x

-------------------------

- [ Generator ]

-------------------------

- en_din_i = x, rdy_din_o = x, din_i = 12

- en_dout_i = x, rdy_dout_o = x, dout_o = x

-------------------------

- [ Generator ]

-------------------------

- en_din_i = x, rdy_din_o = x, din_i = 4

- en_dout_i = x, rdy_dout_o = x, dout_o = x

-------------------------

- [ Generator ]

-------------------------

- en_din_i = x, rdy_din_o = x, din_i = 7

- en_dout_i = x, rdy_dout_o = x, dout_o = x

-------------------------

- [ Generator ]

-------------------------

- en_din_i = x, rdy_din_o = x, din_i = 13

- en_dout_i = x, rdy_dout_o = x, dout_o = x

-------------------------

- [ Generator ]

-------------------------

- en_din_i = x, rdy_din_o = x, din_i = 11

- en_dout_i = x, rdy_dout_o = x, dout_o = x

-------------------------

- [ Generator ]

-------------------------

- en_din_i = x, rdy_din_o = x, din_i = 1

- en_dout_i = x, rdy_dout_o = x, dout_o = x

-------------------------

- [ Generator ]

-------------------------

- en_din_i = x, rdy_din_o = x, din_i = 6

- en_dout_i = x, rdy_dout_o = x, dout_o = x

-------------------------

- [ Generator ]

-------------------------

- en_din_i = x, rdy_din_o = x, din_i = 3

- en_dout_i = x, rdy_dout_o = x, dout_o = x

-------------------------

- [ Generator ]

-------------------------

- en_din_i = x, rdy_din_o = x, din_i = 2

- en_dout_i = x, rdy_dout_o = x, dout_o = x

-------------------------

- [ Generator ]

-------------------------

- en_din_i = x, rdy_din_o = x, din_i = 11

- en_dout_i = x, rdy_dout_o = x, dout_o = x

-------------------------

- [ Generator ]

-------------------------

- en_din_i = x, rdy_din_o = x, din_i = 1

- en_dout_i = x, rdy_dout_o = x, dout_o = x

-------------------------

- [ Generator ]

-------------------------

- en_din_i = x, rdy_din_o = x, din_i = 9

- en_dout_i = x, rdy_dout_o = x, dout_o = x

-------------------------

- [ Generator ]

-------------------------

- en_din_i = x, rdy_din_o = x, din_i = 2

- en_dout_i = x, rdy_dout_o = x, dout_o = x

-------------------------

- [ Generator ]

-------------------------

- en_din_i = x, rdy_din_o = x, din_i = 11

- en_dout_i = x, rdy_dout_o = x, dout_o = x

-------------------------

- [ Generator ]

-------------------------

- en_din_i = x, rdy_din_o = x, din_i = 12

- en_dout_i = x, rdy_dout_o = x, dout_o = x

-------------------------

- [ Generator ]

-------------------------

- en_din_i = x, rdy_din_o = x, din_i = 1

- en_dout_i = x, rdy_dout_o = x, dout_o = x

-------------------------

- [ Generator ]

-------------------------

- en_din_i = x, rdy_din_o = x, din_i = 0

- en_dout_i = x, rdy_dout_o = x, dout_o = x

-------------------------

- [ Generator ]

-------------------------

- en_din_i = x, rdy_din_o = x, din_i = 15

- en_dout_i = x, rdy_dout_o = x, dout_o = x

-------------------------

- [ Generator ]

-------------------------

- en_din_i = x, rdy_din_o = x, din_i = 3

- en_dout_i = x, rdy_dout_o = x, dout_o = x

-------------------------

- [ Generator ]

-------------------------

- en_din_i = x, rdy_din_o = x, din_i = 5

- en_dout_i = x, rdy_dout_o = x, dout_o = x

-------------------------

- [ Generator ]

-------------------------

- en_din_i = x, rdy_din_o = x, din_i = 1

- en_dout_i = x, rdy_dout_o = x, dout_o = x

-------------------------

- [ Generator ]

-------------------------

- en_din_i = x, rdy_din_o = x, din_i = 15

- en_dout_i = x, rdy_dout_o = x, dout_o = x

-------------------------

- [ Generator ]

-------------------------

- en_din_i = x, rdy_din_o = x, din_i = 14

- en_dout_i = x, rdy_dout_o = x, dout_o = x

-------------------------

- [ Generator ]

-------------------------

- en_din_i = x, rdy_din_o = x, din_i = 6

- en_dout_i = x, rdy_dout_o = x, dout_o = x

-------------------------

- [ Generator ]

-------------------------

- en_din_i = x, rdy_din_o = x, din_i = 5

- en_dout_i = x, rdy_dout_o = x, dout_o = x

-------------------------

- [ Generator ]

-------------------------

- en_din_i = x, rdy_din_o = x, din_i = 6

- en_dout_i = x, rdy_dout_o = x, dout_o = x

-------------------------

- [ Generator ]

-------------------------

- en_din_i = x, rdy_din_o = x, din_i = 12

- en_dout_i = x, rdy_dout_o = x, dout_o = x

-------------------------

- [ Generator ]

-------------------------

- en_din_i = x, rdy_din_o = x, din_i = 12

- en_dout_i = x, rdy_dout_o = x, dout_o = x

-------------------------

- [ Generator ]

-------------------------

- en_din_i = x, rdy_din_o = x, din_i = 11

- en_dout_i = x, rdy_dout_o = x, dout_o = x

-------------------------

- [ Generator ]

-------------------------

- en_din_i = x, rdy_din_o = x, din_i = 11

- en_dout_i = x, rdy_dout_o = x, dout_o = x

-------------------------

- [ Generator ]

-------------------------

- en_din_i = x, rdy_din_o = x, din_i = 13

- en_dout_i = x, rdy_dout_o = x, dout_o = x

-------------------------

- [ Generator ]

-------------------------

- en_din_i = x, rdy_din_o = x, din_i = 13

- en_dout_i = x, rdy_dout_o = x, dout_o = x

-------------------------

- [ Generator ]

-------------------------

- en_din_i = x, rdy_din_o = x, din_i = 6

- en_dout_i = x, rdy_dout_o = x, dout_o = x

-------------------------

- [ Generator ]

-------------------------

- en_din_i = x, rdy_din_o = x, din_i = 4

- en_dout_i = x, rdy_dout_o = x, dout_o = x

-------------------------

- [ Generator ]

-------------------------

- en_din_i = x, rdy_din_o = x, din_i = 7

- en_dout_i = x, rdy_dout_o = x, dout_o = x

-------------------------

- [ Generator ]

-------------------------

- en_din_i = x, rdy_din_o = x, din_i = 15

- en_dout_i = x, rdy_dout_o = x, dout_o = x

-------------------------

- [ Generator ]

-------------------------

- en_din_i = x, rdy_din_o = x, din_i = 11

- en_dout_i = x, rdy_dout_o = x, dout_o = x

-------------------------

- [ Generator ]

-------------------------

- en_din_i = x, rdy_din_o = x, din_i = 11

- en_dout_i = x, rdy_dout_o = x, dout_o = x

-------------------------

- [ Generator ]

-------------------------

- en_din_i = x, rdy_din_o = x, din_i = 4

- en_dout_i = x, rdy_dout_o = x, dout_o = x

-------------------------

- [ Generator ]

-------------------------

- en_din_i = x, rdy_din_o = x, din_i = 14

- en_dout_i = x, rdy_dout_o = x, dout_o = x

-------------------------

- [ Generator ]

-------------------------

- en_din_i = x, rdy_din_o = x, din_i = 11

- en_dout_i = x, rdy_dout_o = x, dout_o = x

-------------------------

- [ Generator ]

-------------------------

- en_din_i = x, rdy_din_o = x, din_i = 2

- en_dout_i = x, rdy_dout_o = x, dout_o = x

-------------------------

- [ Generator ]

-------------------------

- en_din_i = x, rdy_din_o = x, din_i = 9

- en_dout_i = x, rdy_dout_o = x, dout_o = x

-------------------------

- [ Generator ]

-------------------------

- en_din_i = x, rdy_din_o = x, din_i = 1

- en_dout_i = x, rdy_dout_o = x, dout_o = x

-------------------------

- [ Generator ]

-------------------------

- en_din_i = x, rdy_din_o = x, din_i = 10

- en_dout_i = x, rdy_dout_o = x, dout_o = x

-------------------------

- [ Generator ]

-------------------------

- en_din_i = x, rdy_din_o = x, din_i = 5

- en_dout_i = x, rdy_dout_o = x, dout_o = x

-------------------------

- [ Generator ]

-------------------------

- en_din_i = x, rdy_din_o = x, din_i = 9

- en_dout_i = x, rdy_dout_o = x, dout_o = x

-------------------------

- [ Generator ]

-------------------------

- en_din_i = x, rdy_din_o = x, din_i = 0

- en_dout_i = x, rdy_dout_o = x, dout_o = x

-------------------------

- [ Generator ]

-------------------------

- en_din_i = x, rdy_din_o = x, din_i = 13

- en_dout_i = x, rdy_dout_o = x, dout_o = x

-------------------------

- [ Generator ]

-------------------------

- en_din_i = x, rdy_din_o = x, din_i = 7

- en_dout_i = x, rdy_dout_o = x, dout_o = x

-------------------------

- [ Generator ]

-------------------------

- en_din_i = x, rdy_din_o = x, din_i = 5

- en_dout_i = x, rdy_dout_o = x, dout_o = x

-------------------------

- [ Generator ]

-------------------------

- en_din_i = x, rdy_din_o = x, din_i = 9

- en_dout_i = x, rdy_dout_o = x, dout_o = x

-------------------------

- [ Generator ]

-------------------------

- en_din_i = x, rdy_din_o = x, din_i = 10

- en_dout_i = x, rdy_dout_o = x, dout_o = x

-------------------------

- [ Generator ]

-------------------------

- en_din_i = x, rdy_din_o = x, din_i = 4

- en_dout_i = x, rdy_dout_o = x, dout_o = x

-------------------------

- [ Generator ]

-------------------------

- en_din_i = x, rdy_din_o = x, din_i = 5

- en_dout_i = x, rdy_dout_o = x, dout_o = x

-------------------------

- [ Generator ]

-------------------------

- en_din_i = x, rdy_din_o = x, din_i = 6

- en_dout_i = x, rdy_dout_o = x, dout_o = x

-------------------------

- [ Generator ]

-------------------------

- en_din_i = x, rdy_din_o = x, din_i = 11

- en_dout_i = x, rdy_dout_o = x, dout_o = x

-------------------------

- [ Generator ]

-------------------------

- en_din_i = x, rdy_din_o = x, din_i = 4

- en_dout_i = x, rdy_dout_o = x, dout_o = x

-------------------------

- [ Generator ]

-------------------------

- en_din_i = x, rdy_din_o = x, din_i = 5

- en_dout_i = x, rdy_dout_o = x, dout_o = x

-------------------------

- [ Generator ]

-------------------------

- en_din_i = x, rdy_din_o = x, din_i = 0

- en_dout_i = x, rdy_dout_o = x, dout_o = x

-------------------------

- [ Generator ]

-------------------------

- en_din_i = x, rdy_din_o = x, din_i = 8

- en_dout_i = x, rdy_dout_o = x, dout_o = x

-------------------------

- [ Generator ]

-------------------------

- en_din_i = x, rdy_din_o = x, din_i = 0

- en_dout_i = x, rdy_dout_o = x, dout_o = x

-------------------------

- [ Generator ]

-------------------------

- en_din_i = x, rdy_din_o = x, din_i = 5

- en_dout_i = x, rdy_dout_o = x, dout_o = x

-------------------------

- [ Generator ]

-------------------------

- en_din_i = x, rdy_din_o = x, din_i = 8

- en_dout_i = x, rdy_dout_o = x, dout_o = x

-------------------------

- [ Generator ]

-------------------------

- en_din_i = x, rdy_din_o = x, din_i = 13

- en_dout_i = x, rdy_dout_o = x, dout_o = x

-------------------------

- [ Generator ]

-------------------------

- en_din_i = x, rdy_din_o = x, din_i = 4

- en_dout_i = x, rdy_dout_o = x, dout_o = x

-------------------------

- [ Generator ]

-------------------------

- en_din_i = x, rdy_din_o = x, din_i = 14

- en_dout_i = x, rdy_dout_o = x, dout_o = x

-------------------------

- [ Generator ]

-------------------------

- en_din_i = x, rdy_din_o = x, din_i = 11

- en_dout_i = x, rdy_dout_o = x, dout_o = x

-------------------------

- [ Generator ]

-------------------------

- en_din_i = x, rdy_din_o = x, din_i = 15

- en_dout_i = x, rdy_dout_o = x, dout_o = x

-------------------------

- [ Generator ]

-------------------------

- en_din_i = x, rdy_din_o = x, din_i = 2

- en_dout_i = x, rdy_dout_o = x, dout_o = x

-------------------------

- [ Generator ]

-------------------------

- en_din_i = x, rdy_din_o = x, din_i = 8

- en_dout_i = x, rdy_dout_o = x, dout_o = x

-------------------------

- [ Generator ]

-------------------------

- en_din_i = x, rdy_din_o = x, din_i = 4

- en_dout_i = x, rdy_dout_o = x, dout_o = x

-------------------------

- [ Generator ]

-------------------------

- en_din_i = x, rdy_din_o = x, din_i = 13

- en_dout_i = x, rdy_dout_o = x, dout_o = x

-------------------------

- [ Generator ]

-------------------------

- en_din_i = x, rdy_din_o = x, din_i = 10

- en_dout_i = x, rdy_dout_o = x, dout_o = x

-------------------------

- [ Generator ]

-------------------------

- en_din_i = x, rdy_din_o = x, din_i = 11

- en_dout_i = x, rdy_dout_o = x, dout_o = x

-------------------------

- [ Generator ]

-------------------------

- en_din_i = x, rdy_din_o = x, din_i = 15

- en_dout_i = x, rdy_dout_o = x, dout_o = x

-------------------------

- [ Generator ]

-------------------------

- en_din_i = x, rdy_din_o = x, din_i = 15

- en_dout_i = x, rdy_dout_o = x, dout_o = x

-------------------------

- [ Generator ]

-------------------------

- en_din_i = x, rdy_din_o = x, din_i = 12

- en_dout_i = x, rdy_dout_o = x, dout_o = x

-------------------------

- [ Generator ]

-------------------------

- en_din_i = x, rdy_din_o = x, din_i = 6

- en_dout_i = x, rdy_dout_o = x, dout_o = x

-------------------------

- [ Generator ]

-------------------------

- en_din_i = x, rdy_din_o = x, din_i = 1

- en_dout_i = x, rdy_dout_o = x, dout_o = x

-------------------------

- [ Generator ]

-------------------------

- en_din_i = x, rdy_din_o = x, din_i = 9

- en_dout_i = x, rdy_dout_o = x, dout_o = x

-------------------------

- [ Generator ]

-------------------------

- en_din_i = x, rdy_din_o = x, din_i = 4

- en_dout_i = x, rdy_dout_o = x, dout_o = x

-------------------------

- [ Generator ]

-------------------------

- en_din_i = x, rdy_din_o = x, din_i = 12

- en_dout_i = x, rdy_dout_o = x, dout_o = x

-------------------------

- [ Generator ]

-------------------------

- en_din_i = x, rdy_din_o = x, din_i = 8

- en_dout_i = x, rdy_dout_o = x, dout_o = x

-------------------------

- [ Generator ]

-------------------------

- en_din_i = x, rdy_din_o = x, din_i = 12

- en_dout_i = x, rdy_dout_o = x, dout_o = x

-------------------------

- [ Generator ]

-------------------------

- en_din_i = x, rdy_din_o = x, din_i = 4

- en_dout_i = x, rdy_dout_o = x, dout_o = x

-------------------------

- [ Generator ]

-------------------------

- en_din_i = x, rdy_din_o = x, din_i = 9

- en_dout_i = x, rdy_dout_o = x, dout_o = x

-------------------------

- [ Generator ]

-------------------------

- en_din_i = x, rdy_din_o = x, din_i = 1

- en_dout_i = x, rdy_dout_o = x, dout_o = x

-------------------------

- [ Generator ]

-------------------------

- en_din_i = x, rdy_din_o = x, din_i = 9

- en_dout_i = x, rdy_dout_o = x, dout_o = x

-------------------------

- [ Generator ]

-------------------------

- en_din_i = x, rdy_din_o = x, din_i = 7

- en_dout_i = x, rdy_dout_o = x, dout_o = x

-------------------------

- [ Generator ]

-------------------------

- en_din_i = x, rdy_din_o = x, din_i = 10

- en_dout_i = x, rdy_dout_o = x, dout_o = x

-------------------------

- [ Generator ]

-------------------------

- en_din_i = x, rdy_din_o = x, din_i = 6

- en_dout_i = x, rdy_dout_o = x, dout_o = x

-------------------------

- [ Generator ]

-------------------------

- en_din_i = x, rdy_din_o = x, din_i = 11

- en_dout_i = x, rdy_dout_o = x, dout_o = x

-------------------------

- [ Driver ]

-------------------------

- en_din_i = 1, rdy_din_o = 0, din_i = 13

- en_dout_i = x, rdy_dout_o = x, dout_o = x

-------------------------

- [ Monitor ]

-------------------------

- en_din_i = x, rdy_din_o = x, din_i = 13

- en_dout_i = x, rdy_dout_o = x, dout_o = 13

-------------------------

Result is as Expected

-------------------------

- [ Scoreboard ]

-------------------------

- en_din_i = x, rdy_din_o = x, din_i = 13

- en_dout_i = x, rdy_dout_o = x, dout_o = 13

-------------------------

- [ Driver ]

-------------------------

- en_din_i = 1, rdy_din_o = 0, din_i = 6

- en_dout_i = x, rdy_dout_o = x, dout_o = x

-------------------------

- [ Monitor ]

-------------------------

- en_din_i = x, rdy_din_o = x, din_i = 6

- en_dout_i = x, rdy_dout_o = x, dout_o = 6

-------------------------

Result is as Expected

-------------------------

- [ Scoreboard ]

-------------------------

- en_din_i = x, rdy_din_o = x, din_i = 6

- en_dout_i = x, rdy_dout_o = x, dout_o = 6

-------------------------

- [ Driver ]

-------------------------

- en_din_i = 1, rdy_din_o = 0, din_i = 15

- en_dout_i = x, rdy_dout_o = x, dout_o = x

-------------------------

- [ Monitor ]

-------------------------

- en_din_i = x, rdy_din_o = x, din_i = 15

- en_dout_i = x, rdy_dout_o = x, dout_o = 15

-------------------------

Result is as Expected

-------------------------

- [ Scoreboard ]

-------------------------

- en_din_i = x, rdy_din_o = x, din_i = 15

- en_dout_i = x, rdy_dout_o = x, dout_o = 15

-------------------------

- [ Driver ]

-------------------------

- en_din_i = 1, rdy_din_o = 0, din_i = 15

- en_dout_i = x, rdy_dout_o = x, dout_o = x

-------------------------

- [ Monitor ]

-------------------------

- en_din_i = x, rdy_din_o = x, din_i = 15

- en_dout_i = x, rdy_dout_o = x, dout_o = 15

-------------------------

Result is as Expected ( ETC. ETC.)

-------------------------

- [ Scoreboard ]

-------------------------

- en_din_i = x, rdy_din_o = x, din_i = 15

- en_dout_i = x, rdy_dout_o = x, dout_o = 15

-------------------------

- [ Driver ]

-------------------------

- en_din_i = 1, rdy_din_o = 0, din_i = 7

- en_dout_i = x, rdy_dout_o = x, dout_o = x

-------------------------

- [ Monitor ]

-------------------------

- en_din_i = x, rdy_din_o = x, din_i = 7

- en_dout_i = x, rdy_dout_o = x, dout_o = 7

-------------------------

Result is as Expected

-------------------------

- [ Scoreboard ]

-------------------------

- en_din_i = x, rdy_din_o = x, din_i = 7

- en_dout_i = x, rdy_dout_o = x, dout_o = 7

-------------------------

- [ Driver ]

-------------------------

- en_din_i = 1, rdy_din_o = 0, din_i = 15

- en_dout_i = x, rdy_dout_o = x, dout_o = x

-------------------------

- [ Monitor ]

-------------------------

- en_din_i = x, rdy_din_o = x, din_i = 15

- en_dout_i = x, rdy_dout_o = x, dout_o = 15

-------------------------

Result is as Expected

-------------------------

- [ Scoreboard ]

-------------------------

- en_din_i = x, rdy_din_o = x, din_i = 15

- en_dout_i = x, rdy_dout_o = x, dout_o = 15

-------------------------

- [ Driver ]

-------------------------

- en_din_i = 1, rdy_din_o = 0, din_i = 4

- en_dout_i = x, rdy_dout_o = x, dout_o = x

-------------------------

- [ Monitor ]

-------------------------

- en_din_i = x, rdy_din_o = x, din_i = 4

- en_dout_i = x, rdy_dout_o = x, dout_o = 4

-------------------------

Result is as Expected

-------------------------

- [ Scoreboard ]

-------------------------

- en_din_i = x, rdy_din_o = x, din_i = 4

- en_dout_i = x, rdy_dout_o = x, dout_o = 4

-------------------------

- [ Driver ]

-------------------------

- en_din_i = 1, rdy_din_o = 0, din_i = 12

- en_dout_i = x, rdy_dout_o = x, dout_o = x

-------------------------

- [ Monitor ]

-------------------------

- en_din_i = x, rdy_din_o = x, din_i = 12

- en_dout_i = x, rdy_dout_o = x, dout_o = 12

-------------------------

Result is as Expected

-------------------------

- [ Scoreboard ]

-------------------------

- en_din_i = x, rdy_din_o = x, din_i = 12

- en_dout_i = x, rdy_dout_o = x, dout_o = 12

-------------------------

- [ Driver ]

-------------------------

- en_din_i = 1, rdy_din_o = 0, din_i = 4

- en_dout_i = x, rdy_dout_o = x, dout_o = x

-------------------------

- [ Monitor ]

-------------------------

- en_din_i = x, rdy_din_o = x, din_i = 4

- en_dout_i = x, rdy_dout_o = x, dout_o = 4

-------------------------

Result is as Expected

-------------------------

- [ Scoreboard ]

-------------------------

- en_din_i = x, rdy_din_o = x, din_i = 4

- en_dout_i = x, rdy_dout_o = x, dout_o = 4

-------------------------

- [ Driver ]

-------------------------

- en_din_i = 1, rdy_din_o = 0, din_i = 7

- en_dout_i = x, rdy_dout_o = x, dout_o = x

-------------------------

- [ Monitor ]

-------------------------

- en_din_i = x, rdy_din_o = x, din_i = 7

- en_dout_i = x, rdy_dout_o = x, dout_o = 7

-------------------------

Result is as Expected

-------------------------

- [ Scoreboard ]

-------------------------

- en_din_i = x, rdy_din_o = x, din_i = 7

- en_dout_i = x, rdy_dout_o = x, dout_o = 7

-------------------------

- [ Driver ]

-------------------------

- en_din_i = 1, rdy_din_o = 0, din_i = 13

- en_dout_i = x, rdy_dout_o = x, dout_o = x

-------------------------

- [ Monitor ]

-------------------------

- en_din_i = x, rdy_din_o = x, din_i = 13

- en_dout_i = x, rdy_dout_o = x, dout_o = 13

-------------------------

Result is as Expected

-------------------------

- [ Scoreboard ]

-------------------------

- en_din_i = x, rdy_din_o = x, din_i = 13

- en_dout_i = x, rdy_dout_o = x, dout_o = 13

-------------------------

- [ Driver ]

-------------------------

- en_din_i = 1, rdy_din_o = 0, din_i = 11

- en_dout_i = x, rdy_dout_o = x, dout_o = x

-------------------------

- [ Monitor ]

-------------------------

- en_din_i = x, rdy_din_o = x, din_i = 11

- en_dout_i = x, rdy_dout_o = x, dout_o = 11

-------------------------

Result is as Expected

-------------------------

- [ Scoreboard ]

-------------------------

- en_din_i = x, rdy_din_o = x, din_i = 11

- en_dout_i = x, rdy_dout_o = x, dout_o = 11

-------------------------

- [ Driver ]

-------------------------

- en_din_i = 1, rdy_din_o = 0, din_i = 1

- en_dout_i = x, rdy_dout_o = x, dout_o = x

-------------------------

- [ Monitor ]

-------------------------

- en_din_i = x, rdy_din_o = x, din_i = 1

- en_dout_i = x, rdy_dout_o = x, dout_o = 1

-------------------------

Result is as Expected

-------------------------

- [ Scoreboard ]

-------------------------

- en_din_i = x, rdy_din_o = x, din_i = 1

- en_dout_i = x, rdy_dout_o = x, dout_o = 1

-------------------------

- [ Driver ]

-------------------------

- en_din_i = 1, rdy_din_o = 0, din_i = 6

- en_dout_i = x, rdy_dout_o = x, dout_o = x

-------------------------

- [ Monitor ]

-------------------------

- en_din_i = x, rdy_din_o = x, din_i = 6

- en_dout_i = x, rdy_dout_o = x, dout_o = 6

-------------------------

Result is as Expected

-------------------------

- [ Scoreboard ]

-------------------------

- en_din_i = x, rdy_din_o = x, din_i = 6

- en_dout_i = x, rdy_dout_o = x, dout_o = 6

-------------------------

- [ Driver ]

-------------------------

- en_din_i = 1, rdy_din_o = 0, din_i = 3

- en_dout_i = x, rdy_dout_o = x, dout_o = x

-------------------------

- [ Monitor ]

-------------------------

- en_din_i = x, rdy_din_o = x, din_i = 3

- en_dout_i = x, rdy_dout_o = x, dout_o = 3

-------------------------

Result is as Expected

-------------------------

- [ Scoreboard ]

-------------------------

- en_din_i = x, rdy_din_o = x, din_i = 3

- en_dout_i = x, rdy_dout_o = x, dout_o = 3

-------------------------

- [ Driver ]

-------------------------

- en_din_i = 1, rdy_din_o = 0, din_i = 2

- en_dout_i = x, rdy_dout_o = x, dout_o = x

-------------------------

- [ Monitor ]

-------------------------

- en_din_i = x, rdy_din_o = x, din_i = 2

- en_dout_i = x, rdy_dout_o = x, dout_o = 2

-------------------------

Result is as Expected

-------------------------

- [ Scoreboard ]

-------------------------

- en_din_i = x, rdy_din_o = x, din_i = 2

- en_dout_i = x, rdy_dout_o = x, dout_o = 2

-------------------------

- [ Driver ]

-------------------------

- en_din_i = 1, rdy_din_o = 0, din_i = 11

- en_dout_i = x, rdy_dout_o = x, dout_o = x

-------------------------

- [ Monitor ]

-------------------------

- en_din_i = x, rdy_din_o = x, din_i = 11

- en_dout_i = x, rdy_dout_o = x, dout_o = 11

-------------------------

Result is as Expected

-------------------------

- [ Scoreboard ]

-------------------------

- en_din_i = x, rdy_din_o = x, din_i = 11

- en_dout_i = x, rdy_dout_o = x, dout_o = 11

-------------------------

- [ Driver ]

-------------------------

- en_din_i = 1, rdy_din_o = 0, din_i = 1

- en_dout_i = x, rdy_dout_o = x, dout_o = x

-------------------------

- [ Monitor ]

-------------------------

- en_din_i = x, rdy_din_o = x, din_i = 1

- en_dout_i = x, rdy_dout_o = x, dout_o = 1

-------------------------

Result is as Expected

-------------------------

- [ Scoreboard ]

-------------------------

- en_din_i = x, rdy_din_o = x, din_i = 1

- en_dout_i = x, rdy_dout_o = x, dout_o = 1

-------------------------

- [ Driver ]

-------------------------

- en_din_i = 1, rdy_din_o = 0, din_i = 9

- en_dout_i = x, rdy_dout_o = x, dout_o = x

-------------------------

- [ Monitor ]

-------------------------

- en_din_i = x, rdy_din_o = x, din_i = 9

- en_dout_i = x, rdy_dout_o = x, dout_o = 9

-------------------------

Result is as Expected

-------------------------

- [ Scoreboard ]

-------------------------

- en_din_i = x, rdy_din_o = x, din_i = 9

- en_dout_i = x, rdy_dout_o = x, dout_o = 9

-------------------------

- [ Driver ]

-------------------------

- en_din_i = 1, rdy_din_o = 0, din_i = 2

- en_dout_i = x, rdy_dout_o = x, dout_o = x

-------------------------

- [ Monitor ]

-------------------------

- en_din_i = x, rdy_din_o = x, din_i = 2

- en_dout_i = x, rdy_dout_o = x, dout_o = 2

-------------------------

Result is as Expected

-------------------------

- [ Scoreboard ]

-------------------------

- en_din_i = x, rdy_din_o = x, din_i = 2

- en_dout_i = x, rdy_dout_o = x, dout_o = 2

-------------------------

Simulation stopped after 500 clock cycles

$finish called from file "testbench.sv", line 65.

$finish at simulation time 4995

V C S S i m u l a t i o n R e p o r t

Time: 4995 ns

CPU Time: 0.540 seconds; Data structure size: 0.0Mb

Mon Jul 17 09:41:42 2023

Finding VCD file...

./dump.vcd

[2023-07-17 13:41:42 UTC] Opening EPWave...

Done

ASIC Stoic

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Monday, July 17, 2023

UVM like (non-UVM) verification environment verifying a DUT with handshake controlled input and output

Introduction

Verification environment architecture

Individual functioning (and interconnection between them), of all verification architecture elements

DUT

Interface

testbench.sv ( top testbench module )

Transaction Class

Generator Class

Driver Class

Environment Class

Test Program

Monitor Class

Scoreboard Class

Verification waveforms

Simulation/Verification log

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