NMOS current mirror: Importance of increased output resistance and how to do it

In one of the previous blog entries http://asicstoic.blogspot.fr/2015/04/analog-design-basics-nmos.html it is introduced a typical example of an NMOS transistor usage: a current mirror.

And in the other blog entry http://asicstoic.blogspot.fr/2015/04/analog-design-basics-nmos.html it is introduced a characteristic Ids = f (Vds) of an NMOS transistor and a formula of Ids = f (Vds) in saturation:

Here is another term to define here: “voltage headroom”, meaning what is the minimum Vds to keep a current mirror functioning.

For a simple current mirror a  voltage headroom is defined by minimum Vds to  keep  transistor M2 in active mode ( saturation ):   

Vds = Vgs -Vt

On a different subject,  so far every time we discussed NMOS transistor in saturation mode,  there was an approximation assumed:  in saturation mode Ids is independent of Vds. The approximation is possible under assumption that λ =0 (the channel-length modulation parameter )

In the ideal case when λ =0 that would mean that a change in Vds2 will not affect Ids2 ( ds2/Ids2 = infinity . This brings us to concept of r0 “output resistance” of the NMOS current mirror that in ideal case should be infinity large.

Obviously in our current mirror design we would like to achieve r0 as large as possible and can be proven that NMOS transistor r0 is  approximately:

r0 = 1 * Ids    and   λ = 1/L

For a simple CMOS current mirror output resistance r0 is equal rds2.

One simple way to increase output resistance of a current mirror is to use following schematic, named “source-degenerated current mirror”

  

Here is necessary to introduce a concept of: transistor transconductance ( gm )

Transistor transconductance ( gm )  in transistor active region ( when Ids is independent of Vds )  how much Id changes with change of Vgs:

gm = ∂ID/∂VGS

And it can be proven that:

gm =  μn * Cox *  ( W/L ) *  Veff          or

 

• useful in circuit analysis when device sizes are fixed
• increasing Id implies proportional increase W/L  ( if Veff is kept constant )

gm =  2 * ID / Veff                   ( useful in initial circuit design when transistor sizes are yet to be  

                                                  determined )

It can be proven that  a current mirror with source degradation has output resistance increased (1 + Rs*gm2) times comparing to a simple current mirror.    

In other words when a small-signal resistance Rs is introduced at the source of both transistors in a simple current mirror, the output resistance is increased (1 + Rs*gm) times .  

One of the major topologies of a current mirrors with increased output resistance is : “ a cascode current mirror “

First, note that the output resistance looking into the drain of Q2 is simply rds2 ( a simple current mirror ).

Second Q4 transistor should be considered  as a current source with a source-degeneration resistor of value rds4.

Finally, output resistance of the cascode current mirror is :

rout = rds4[1 + rds2*gm4] ≅ rds4*(rds2*gm4)

Conclusion here is that the addition of a cascode device to a CMOS current mirror

increases its output resistance by approximately the gain of the cascode device (Q4) multiplied by rds4 ( rds4*gm4 ) .

A disadvantage of using a cascode current mirror is a reduced “voltage headroom”.

Let’s assume that all transistors of a cascode current mirror have the same sizes and ( by the virtue of a concept of a current mirror)  the same currents.  Then they will all also have the same Veff  and, therefore, the same gate-source voltages ( because : VGS = Veff + Vt )

VG3 = VGS1 + VGS3 = 2Veff + 2Vt

VDS2 = VG3 – VGS4 = VG3 – (Veff + Vt) = Veff + Vt

Conclusion here is that transistor Q2 ( in a cascode current mirror ) needs a higher voltage Vds2 to get to the edge of a saturation mode then a transistor of a simple current mirror: exactly Vt higher.

Consequently, minimum allowed voltage on output of a cascode current mirror is:

Vout > VDS2 + Veff = 2 * Veff + Vt

again, is Vt  greater than the minimum value of  2 * Veff.

© 2011 ASIC Stoic. All rights reserved.

NMOS: A Transistor sizing example

In one of the previous blog entries http://asicstoic.blogspot.fr/2015/04/analog-design-basics-nmos.html it is introduced a typical example of an NMOS transistor usage: a current mirror.

Here is example how to size NMOS transistors used in a current mirror copying a desired current.

Foundation of a current mirror design is the fact that:

• two identical transistors are used: meaning both have identical characteristics: VT , Kn, λ and W/L ratios

• both transistors are in saturation mode, sharing the same Vgs

 

e.g. Because the gate currents are zero for the MOSFETs, reference current IREF must flow into the drain of M1, which is forced to operate in saturation (pinch-off) by the circuit connection

( VDS1 = VGS1 )

• consequently both transistors carry an identical  Ids current

 

e.g. A  reference current IREF goes through “diode-connected” transistor M1, establishing gate-source voltage VGS. The same VGS  is applied to transistor M2, developing an identical drain current  ID2 = Iout= IREF.

Let’s assume that desired Iref = 10μA.

Here is also  Id/Vds characteristic of the NMOS transistor used and it can be safely assumed that the transistor is saturated if Vgs = Vt + 200mv.

The transistors are in saturation mode so relation of Id and Vgs is:

λ  is often assumed as 0

 

© 2011 ASIC Stoic. All rights reserved.

Analog Design Basics: NMOS

Introduction: Why do we need CMOS transistors ?

A bipolar transistor needs a base current to keep the transistor ON. And this is the main problem for bipolars in spite of the fact that its base current is small in a small signal operation.

When bipolar transistor is used in power applications, as a switch,  the base current could be really high, to keep the transistor ON, adding significantly to a power consumption ( e.g.  a need for a extended battery life in portable electronics …. ).

In CMOS technology there are two complementary types of transistors—n-channel (NMOS) and p-channel (PMOS).

NMOS: How it works ?

NMOS transistor ( n channel device ) has three terminals: gate, source and drain. NMOS conducts with a positive gate voltage, and to distinguish between source and drain terminal: a source has a lower voltage.  

As a positive gate voltage is applied, the gate attracts a negative charge forming a channel of mobile electrons connecting the drain and source regions.

• Vtn ( a threshold voltage for n channel device ) is the minimum positive voltage, when applied to a gate, that makes possible conducting electricity between the drain and source.

NMOS is OFF if Vgs < Vtn ( there is no channel formed and there is no possibility of a current flowing from drain to source  ) .

Consequently  NMOS is ON if Vgs  > Vtn ( the channel is formed and if  Vd  > Vs, there will be a current Ids .

• Veff ( effective gate-source voltage ) is: Vgs -Vtn

NMOS modes of functioning: Linear vs Saturation mode

When NMOS is ON (  Vgs  > Vtn  ) and  Vds << Veff, there is approximately  linear relationship between Vds and Ids ( the linear mode ).

NMOS in Linear mode: Ids as linear function of Vgs

But if  Vds > Veff , the channel charge concentration decreases close to the drain terminal ( the channel becomes pinched off ), making a current Ids constant (saturated ) and independent of further increase of Vds. This is the saturated mode.



NMOS in Saturation mode: Id independent of Vds because ( 1+ λ*Vds ) is approx.1 if Kn= μn * Cox *W/L then a formula of saturation Vgs = f(Id = Iref, Vds) is:

  

NMOS transistor exits linear mode and enters the saturated mode when increasing Vds reaches this point:

Vds(saturated) = Vgs - Vtn = Veff

e.g. NMOS transistor application: Current Mirror

The design of current mirror is based on "copying" current from a precisely defined reference.

In a current mirror both NMOS  transistors are in saturated mode, meaning Ids1 ( equal to Iref ) and Ids2 ( equal to Iout ) are independent of its respective Vds voltages and dependent only on its respective Vgs voltages.

• Vds1 = Vgs1= Vgs2      

Vtn +     2Id1/(Kn*( 1+*Vds1) = Vtn +     2Id2/(Kn*( 1+*Vds2)

Id1/(1+*Vds1) = Id2/(1+*Vds2)

Under assumption that: 1+*Vds1= 1+*Vds2

Id1 = Id2

 © 2011 ASIC Stoic. All rights reserved.