Generic ASIC Mix signal specification: Powering of ASIC’s internal circuits, both analog and digital

For the purpose of the ASIC’s internal powering, the specification is planning three ASIC pads:

• one input external voltage power source 5V (VCC5)  and
• two ports of internally generated and used  voltage powers 2.5V ( connected to capacitors to stabilise internal regulators)  
• one powering analog circuits(V_ANA2_5) and
• the other powering digital circuits(V_DIG2_5)  

Fig. 1 e.g. In automotive system it is possible to have car battery supplying external regulator 5V to supply power to VCC5 pad of the ASIC.

• A note on micro-architecture choices made in the ASIC Mixed signal in Fig1

Assumption done here is that will be necessary to have two voltage regulators separated for powering analog and digital block. The reason  is that digital blocks tend to  produce a lot of noise on its power line. Each regulator  is receiving necessary reference voltages/currents from a bandgap. Also each regulator with need an external capacitance for stabilization.

• Also there is a requirement to detect and report Undervoltage condition on both  V_ANA2_5 and  V_DIG2_5.

Maximum Rating

Maximum rating describes that our ASIC will not get damaged even if V_ANA2_5, V_DIG2_5  voltages goes to extremes: minimum -0.1 and maximum 3.5V.
Guaranty of Maximum Rating  is not guarantee that the ASIC would be operational  unless V_ANA2_5, V_DIG2_5 are in  a normal operational range.

Pad name	Value= Min, Max
V_ANA2_5, V_DIG2_5	-0.1V, 3.5V

Normal operating conditions

Pad name	Value= Min, Typ,  Max
V_ANA2_5, V_DIG2_5	2V, 2.5V, 3V

Note: During normal operation for the purpose of the ASIC functionality here is specified that  ASIC will always produce voltages V_ANA2_5, V_DIG2_5 in the range of 2-3V, and typical or average value should be 2.5V.

Undervoltage condition

The ASIC should monitor and report Undervoltage condition on either one of voltage V_ANA2_5, V_DIG2_5.
In the case of Undervoltage condition on either one of V_ANA2_5, V_DIG2_5 , a register flag v2_5_uv is set  and accessible by MPU after power VCC5 is restored to the ASIC .
Once set, the register flag v2_5_uv stays 1 until there is MPU read. The read clears the flag.

Undervoltage  condition  (V_ANA2_5_uv, V_DIG2_5_uv) ,  and filter time (tV2_5_uv)

The V_ANA2_5_uv, V_DIG2_5_uv Undervoltage condition is detected ( and the register flag v2_5_uv is set ) if either one of V_ANA2_5_uv, V_DIG2_5_uv  voltage is LESS then  min=1.5V and max=2.1V ( typical value 1.7V ) , and this event is uninterrupted tV2_5_uv time, value 0.5us.

Parameter description	Parameter Symbol	Value: min, typ, max V	Comment
Undervoltage  fault	V_ANA2_5_uv, V_DIG2_5_uv	1.5, 1.7, 2.1V

The V_ANA2_5_uv, V_DIG2_5_uv Undervoltage condition is considered not present any more if once detected,  both V_ANA2_5, V_DIG2_5  voltages is  MORE then V_ANA2_5_uv, V_DIG2_5_uv , and this event is uninterrupted tV2_5_uv, value 0.5us.

The time tV2_5_uv=0.5us of detection/cancellation of V_ANA2_5_uv, V_DIG2_5_uv Undervoltage condition  is called Undervoltage detection filter time.

Parameter description	Parameter Symbol	Value:typ	Comment
Undervoltage detection filter time	V2_5_uv	0.5us	The filter not possible to implement in digital block: digital power undervoltage is Power on Reset (POR) for digital block. Please see blog post: How to implement a generic ASIC Mix signal: An analog circuit for a glitch free Power-On-Reset signal for Digital block

 
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