Here are some implementation details related to the specification outlined in the other blog entry:Generic ASIC Mix signal specification: An analog circuit for a glitch free Power-On-Reset signal for Digital block ( referred as “Specification”).

One possible solution involves: RC parallel circuit and Common source stage with NMOS

RC parallel circuit

Notice here that after closing the switch VC is climbing immediately to VBAT while after opening the switch, capacitor is slowly discharging trough resitor R.

Common source stage with NMOS.

Here are some well known, basic Voltages and Current dependencies of the circuit.

Without going to much details here is some basic explanation how basic Voltages and Current change in Common source stage with NMOS :

· If VIN = 0, NMOS is not conducting so ID=0 and consequently VOUT= VDD.

· if VIN starts to increase voltage, ID starts to appear and increase in value too while VOUT falls in voltage because VOUT = VDD - ID*R.

· if VIN continue to grow it voltage, at the point when VIN - Vth = VOUT, VOUT is getting closer to 0V, and ID to its max. value ID=VDD/R

Finally here is an implementation hint for our analog circuit:

Here is an explanation what happens to ana_out voltage when Switch (SW) is manipulated:

Lets assume at the beginning SW was closed for a reasonable long time so capacitor ( in the same time gate of NMOS) is for sure fully charged on VDD.

Consequently NMOS is conducting with ID = I through Rd= max value of VDD/Rd so the input of inverter is 0 (VDD – IRd*Rd) and ana_out = 1

Now lets open the SW: Capacitor is discharging with the the current through R (this will take some time)

VC= Vgate, source voltage is falling,IRd is falling too so NMOS is conducting in linear mode and input of inverter voltage is rising.
While C is discharging, VC=Vgate, source voltage is getting smaller, IRd is getting smaller too so at one point: VC-Vth= ana_out, and IRd is getting very close to 0.

At that moment NMOS is not conducting any more and input of inverter voltage becomes very close to VDD and ana_out = 0.

Now lets close the SW: Capacitor is charged immediately to VDD (Vgate, source = VDD immediately and NMOS starts conducting immediately in saturation mode with maximum current ) so input of inverter voltage goes immediately to 0V, and ana_out = 1.

We could improve the design by replacing both resistors with reference current sources, mirrored and/or derived from a “ golden reference”. Also instead of switch we could use PMOS in common drain configuration (“source follower”).