Simple testbench (done in both System Verilog and Verilog HDL) for a Digital design block (Verilog HDL) verification

Lets assume that we have  to verify a basic memory design block done in behavior Verilog HDL (memory.v ) .

memory.v  is done here in Verilog HDL and NOT in System Verilog for legacy reasons:

• it is certain that we can synthesise Verilog HDL RTL design and gate level design that is result of synthesis will also be in Verilog HDL.

/////////////////
/// DUT
///////////////
module memory(
address,
data_in,
data_out,
read_write,
chip_en
);

input [7:0] address, data_in;
output[7:0] data_out;
input read_write, chip_en;

reg [7:0] data_out ;
reg [7:0] mem [0:255];

always @ (address or data_in or read_write or chip_en)
if (read_write == 1 && chip_en == 1) begin
 mem[address] = data_in;
end

always @ (read_write or chip_en or address)
if (read_write == 0 && chip_en)
 data_out = mem[address];
else
 data_out = 0;

endmodule
    
Here is a simple testbench enviroment first done in Verilog HDL and in System Verilog.

Testbench enviroment done in Verilog HDL

////////////////////////////
// Testbench
////////////////////////////
module Testbench(
                             address,
            data_in,
            data_out,
            read_write,
            chip_en
           );

output [7:0] address, data_in;
input  [7:0] data_out;
output       read_write, chip_en;

reg [7:0] address, data_in;
reg       read_write, chip_en;

initial
     begin
        address           = 0 ;
        data_in             = 0 ;
        read_write = 0 ;
        chip_en            = 0 ;

        repeat(3)
            begin
              
               #100  
               chip_en            = 1 ;
               address           = $random ;
               data_in             = $random  ;  
               read_write  =  1’b1 ;
              
               #100
                read_write  =  1’b0 ;
             end

#100
chip_en            = 0 ;

#100
        $finish;

     end // initial

  endmodule

        
        
///////////////////////////////////////////////////////////////////////////////
// top module: integrating Dut and it’s Testbench
///////////////////////////////////////////////////////////////////////////////

module top();
       wire [7:0] address, data_in;
  wire [7:0] data_out;
  wire       read_write, chip_en;

       memory D (
                    .address    ( address    ),
        .data_in    ( data_in    ),
         .data_out   ( data_out   ),
         .read_write ( read_write ),
         .chip_en    ( chip_en    )
               );

     Testbench tb (
                         .address    ( address    ),
               .data_in    ( data_in    ),
               .data_out   ( data_out   ),
               .read_write ( read_write ),
               .chip_en    ( chip_en     )
           );
           
endmodule

Testbench enviroment done in System Verilog

Simulate with Cadence tools  with the command:

irun -access +r -gui  top.sv




////////////////////////////////////////////////////////////////////////////////////////////////
// Interface: for communication between Dut and it’s Testbench
////////////////////////////////////////////////////////////////////////////////////////////////

`ifndef GUARD_INTERFACE
`define GUARD_INTERFACE
interface intf ();

logic read_write, chip_en ;

logic[7:0] address, data_in ;

logic[7:0] data_out ;

modport tb (output read_write, chip_en, address, data_in, input data_out);

endinterface :intf
`endif

///////////////////////////
// Testbench
////////////////////////////
module Testbench(intf tb_if);

initial

begin

tb_if.address =　0 ;

tb_if.data_in = 0 ;

tb_if.read_write = 0 ;

tb_if.chip_en = 0 ;

repeat(3)　begin

#100

tb_if.chip_en = 1 ;

tb_if.address = $random ;

tb_if.data_in = $random ;

tb_if.read_write = 1 ;

#100

tb_if.read_write = 0 ;

end

#100

tb_if.chip_en = 0 ;

#1000

$finish;

end

endmodule


///////////////////////////////////////////////////////////////////////////////
// top module ( top.sv ): integrating Dut and it’s Testbench
////////////////////////////////////////////////////////////////////////////
        
        
`ifndef GUARD_TOP
`define GUARD_TOP
　
module top();
　

intf bus_if(); //interface instantiation

Testbench tb (

.tb_if( bus_if )

        ) ; // Pass the modport into the module

memory d (

.address ( bus_if.address ), // connect the verilog

.data_in ( bus_if.data_in ), // RTL port using interface hierarchy signal name.

.data_out ( bus_if.data_out ),

.read_write ( bus_if.read_write ),

.chip_en ( bus_if.chip_en )

);

endmodule : top
`endif