Generic ASIC Mix signal specification: An analog circuit for a glitch free Power-On-Reset signal for Digital block

Digital block, in order to perform it s function as a part of an ASIC Mix signal design,  has always need a minimum two  input signals. One is clock and the other is Power-On-Reset signal (por).

por  can be implemented as Digital block power undervoltage signal. 


One possible implementation , related to the specification outlined here, is described  in the  blog entry:How to implement a generic ASIC Mix signal: An analog circuit for a glitch free Power-On-Reset signal for Digital block


When Digital block is not power-ed por keeps Digital block under reset (not functional). This make sense because if Digital block is not powered correctly it is not able to perform its function.  

por  is specified to be “active low” in other words when its value changes from 1 to 0 (”falling edge” of por ), Digital block will be reset-ed and kept under reset.
On the other hand when por is 1,  Digital block is functional.

Undervoltage detection filter time (t_v2_5_uv)

In designing analog circuit of por  it is important that por changes from 1 to 0 is glitch free.
When por changes from 1 to 0 and stay 0 during Undervoltage detection filter time (tv2_5_uv alredy described  in a previous blog entry.), only then Digital block should perform its reset.
On the other hand there is no need for glitch free signal when Digital block is getting out of POR reset(por changes from 0 to 1).

Assumption here is that  por already exists but is not glitch free, so that is an input (ana_inp) to the analog block specified here. And the output (ana_out) is por glitch free.




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