Verilog AMS: Introduction to the language and basic examples

Verilog-AMS Hardware Description Language (HDL) language defines behavior of analog and mixed-signal systems.

In otherwords using Verilog-AMS  we can model, design and simulate analog and mixed-signal systems.

Modules

The basic building blocks of Verilog-A/MS are modules.

 e.g. Voltage Follower (input voltage shifted 5v)

module voltage_follower_plus5(in, out);

input in;

output out;

voltage in, out; //voltage is a signal flow

                        //discipline similar to

                        //electrical, except it is limited

                        //potential nature only without current( **see: Modeling Notes )

analog begin

V(out) <+ 5.0 + V(in);

end

endmodule

**Modeling Notes

• voltage discipline is defined in disciplines.vams
• voltage discipline  is a signal flow discipline, declared without a flow (as opposed to a conservative discipline)
• and the voltage follower is a signal-flow model 
• signal-flow models can be freely connected to conservative models 
• since in voltage follower model there is no mention of current (electrical’s flow) a voltage discipline is sufficient for the model then more complicateds electrical discipline
• signal-flow disciplines simplify the voltage follower model

 

 e.g. Voltage Amplifier

module voltage_amplifier (out, in);

input in;

output out;

voltage out,

 in;

parameter real GAIN_VOLTAGE_AMLIFIER = 10.0;

analog

V(out) <+ GAIN_VOLTAGE_AMLIFIER * V(in); //V() is the access function for the potential nature

endmodule

e. g. Current Amplifier

module current_amplifier (out, in);

input in;

output out;

current out, // current is a signal flow

 in;  // discipline compatible with

                    // electrical, but having a

      // flow nature only( no potential or voltage)

                   

parameter real GAIN_CURRENT = 10.0;

analog

  I(out) <+ GAIN_CURRENT * I(in); // ** I() is access function for flow nature

endmodule

 

**Modeling Notes

• The electrical discipline defines V as the access function for the potential  and I as the access function for the flow

 

Ports

Ports are the points where connections can be made to the component

• Ports are described by: direction ( input, output or inout)  and the type of the ports( e.g; electrical )

Note on port direction: Since inout is superset of both input and output ports, one might be tempted to use only inout direction. Language wise that is correct but  using input and output ports are considered a good modeling practice because it provides clarity of intent ( the model using input and output ports is easier to read and its function to understand).

Nodes,nets

Nodes are used as interconnection points for ports. One can think of nodes as wires. 
If one node/wire is completely confined within one module that is called a net.

Nodes are declared in a manner very similar to ports but there is no concept of direction of nodes. If one think of nodes as wires it makes sense to declare node as: electrical. ( in most generic case)

e.g. electrical n;

 It is not possible to directly connect one port to another. To connect ports connect them to the same node.

Any number of ports can be connected to a node.

Analog process

The analog keyword introduces an analog process.

An analog process is used to describe the actual behavior ( or continuous time behavior) of the module.

Processes that describe discrete time behavioral in Verilog AMS are inherited from Verilog and they are: initial and always.

e.g.

analog begin

@(above(V(n) – threshold)) begin                // every time voltage of n exeeds threshold ....

if (!first_time) begin                          // display the message but only first 

            $strobe(message);              // time when voltage of n exeeds threshold

first_time = 1;              // otherwise do nothing

end

end

end

The analog process begins with an event statement  : in our example:
@(above(V(n) – threshold)) begin 
..... // a body of event statement

end


Event statement consists of:

• event expression
• consisting of one or more OR-ed event monitors 
• when true generats event   
• the body of event statement ( or action)             
• executed when event is generated

When event of event expression is true, or in otherwords when event monitor detect the event,    the body of event statement is executed.

Event statements in analog processes are non-blocking ( this is deferent then Verilog processes initial and always). 
Verilog AMS code execution does not stop on an event monitor ( on @ <event statement>)  in an analog process, it simply ignores the event statement (except at the instant the event is true) and continue further sequential code execution .

Ground or reference node

Every circuit has one node designated as the ground or reference node

Local access to the reference node is provided through the ground statement.

ground gnd;

In a VerilogAMS model, the ground node always exists and in the case of behavioral models  use acess functions with only one argument:

V(p) = V(p,gnd) 

The other way is to simply give the ground node a name and then use it when constructing a network.

module simple-circuit(ana_inp);

 input ana_inp ; 

electrical ana_inp ;

ground gnd ;

analog

   V(p,gnd )  ......

endmodule

Transition

The function transition or  transition filter is usefull when translating digital  to analog signals especially when connected to capacitor or inductor ( or other dynamic component ).

The dynamic components have  complex behavior when connected to signals consisting of abruptly discontinous waveforms ( or jumps).  

The function transition will take as input a digital signal ( or piecewise constant waveform: constantly valued exept at points where value changes are abrupt ), and smooth it based on further transition function arguments (that are optional): 

• delay

• rise time 

• fall time

  

   

   

   
  

  
  

e.g.

module digital_to_analog (d,a )

input d;

logic d ;

inout a;

electrical a;

analog // Translate from digital to analog ( 3.5V is digital 1,

             //                                      0V is digital 0.

      V(a) <+ transition( d == 1 ? 3.5 : 0.0, <delay>, <rise time>, <fall time> );

endmodule

Contribution statement

Contribution statements are one way that values can be assigned to analog signals.

Analog signal to be modeled is on the left side of a contribution operator, ‘<+’, followed

by an expression on the right side. 

Analog signal to be modeled on the left side is forced to be equal to the value of the expression on the right side.

Features of  contribution statements:

• If there are multiple contributions to the same branch within the same analog process,the contributions accumulate.

For example, given a pair of nodes declared with the electrical discipline, the code

fragment

V(node_A, node_B) <+ exprression_1 ;

V(node_A, node_B) <+ exprression_2 ;

is equivalent to

V(n1, n2) <+ exprression_1 + exprression_ ;

 

• implicit or fixed-point formulation: the value of the target(analog signal to be modeled is on the left side of a contribution operator ) may be expressed in terms of itself in the value of the expression on the right sideof a contribution operator .

 

Example:

l(diode) <+ is*(limexp(V(diode)/$vt – r*l(diode)) –1);

Notice that l(diode) is found on both sides of the contribution operator.

Indirect Branch Assignments

Indirect branch assignments provide onother way how  values can be assigned to analog signals.

  e.g. Ideal Opamp

the output voltage is modeled in such a way  that results in the input voltage being zero

Symplified constitutive equation of an  ideal opamp could be described as:

 

input voltage = 0

The same symplified constitutive equation of an  ideal opamp can be formulated with a contribution statement as

V(out) <+ V(out)+ V(in);

The same equation  represented as  indirect branch assignment is:

V(out): V(in)==0;                // calculate or model  V(out) so that V(in) == 0

 e.g; An ideal opamp.

module ideal_opamp (Vp_out, Vn_out, Vp_in, Vn_in);

output Vp_out, Vn_out;

input Vp_in, Vn_in;

electrical Vp_out, Vn_out, Vp_in, Vn_in;

analog begin

V( Vp_out, Vn_out): V(Vp_in, Vn_in) == 0;

end

endmodule

Analog events: initial_step, final_step, cross, above

The initial_step and final_step events occur on the beginning and end  of a particular
simulation.

If you want to detect more than one kind of event, you can use the event or operator

initial_step

e.g.

analog begin

@(initial_step or cross(V(sample)-2.5, +1)) begin

vout = V(in)  ;

end

V(out) <+ vout ;

end

timer

e.g Module squarewave produces  the output voltage changes from positive 1V to negative (-1V)  and vice versa at every time interval of parameter period/2( in seconds).

module squarewave (out)

output out ;

electrical out ;

parameter period = 1 from(0:inf) ;  // sampling period (s)

integer pcw ;                       // piecewise constant waveform   

analog begin

@(initial_step) pcw = 1 ;

@(timer(0, period/2)) pcw = - pcw ;

// square wave produced has:

// 1)amplitude +/- 1V folowing piecewise constant waveform

// in variable pcw;

//

// 2) no delay relative to piecewise constant waveform

// in variable pcw;

//

// 3)rise time=fall time= period/100( in seconds)

V(out) <+ transition(pcw, 0.0, period/100.0 ) ; // square

end

endmodule

final_step

You might use the event final_step event to print out the results at the end of an simulation analysis.

e.g. module bit_error_rate measures the bit-error of a signal and prints out the results at the end of the analysis. Two input voltages ( in and ref ) sampled at parameter period ( default: 1 second ). One par of samples, sampled at the same period  are considered as: 

• valid bit with value Logic1( if both voltages above parameter threshold  ( default: 5V)  
• valid bit with value Logic0( if both voltages smaller then parameter threshold 
• invalid bit or error ( if one voltage above and another smaller then threshold )   

module bit_error_rate (in, ref) ;

input in, ref ;

electrical in, ref ;

parameter real period    = 1 from(0:inf) ; // sampling period (s)

parameter real threshold = 5 ;

integer bits, errors ;

analog begin

@(initial_step) begin

bits = 0 ;

errors = 0 ; // Initialize the variables

end

@(timer(0, period)) begin

if ((V(in) > threshold) != (V(ref) > threshold))

errors = errors + 1; // Check for errors each period

bits = bits + 1 ;

end

@(final_step)

$strobe("Bit error rate = %f%%", 100.0 * errors/bits );

end

endmodule

Monitoring threshold crossings: cross and above

e.g. Detecting voltage V(p,n) equal to a threshold: trsh
 @(cross(V(p,n) - trsh, 0 )) ;

e.g. Detect first time  V(p,n) equal to a threshold: trsh, and write a message when it happens

@(above(V(p,n) – trsh))
     if (!first_time) begin
         $strobe(message);
          first_time = 1;
     end

Delay

absdelay( <input waveform>, delay)

Returns a waveform that equals the input waveform, delayed in time by an amount

equal to delay, (must be always positive).

                                                                                                               

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