Verilog AMS: Behavioral Interaction of digital and analog blocks ( or processes )

Verilog-AMS supports various types of blocks or processes used to describe mixed signal circuit behavior.

In general, digital behavior is described in initial and always blocks and analog behavior is described in analog blocks.

In a Verilog-AMS module, you can have, at most, one analog block and any

number of initial and always blocks.

The nets and variables of each domain can be referenced in the other context, which is how information passes between the continuous and discrete domains.

Read operations of nets and variables in both domains are allowed from both contexts.

Write operations of nets and variables are only allowed from within the context of their domain,

futher more  a write operation of nets and variables define where a particular net or variable belongs: if written in any of digital blocks it belongs to the digital domain and if written in the analog block it belongs to the analog domain.

• How VerilogAMS handles either digital or analog variables in either one of domains?

e.g; Detect when an input signal (ana_inp) has voltage ABOVE 5V or not. If it does, assign digital variable: dig_above_5v to 1, otherwise keep it as 0.

integer    ana_above;        // an analog-owned variable.

integer    dig_above_5v;     // a digital-owned variable.

electrical ana_inp;

always @( ana_above )begin   // a digital block

if ( ana_above )       // Read the analog variable in the digital context.

dig_above_5v = 1; // Write the digital variable dig_above_5v

                                   // in digital block

if ( !ana_above )

dig_above_5v = 0;

end

analog begin // the analog block

   @ (cross (V(ana_inp) - 5.0, +1 ) )

           ana_above = 1; // Write to the variable above in the

                          // analog  context.

         @ (cross (V(ana_inp) - 5.0, -1 ) )

           ana_above = 0; // above, because written in analog block, is

                          // owned by analog and can be only red in digital

• How to use digital signal in analog domain?

  e.g. How digital signal ( signal written in a digital block ) dig_inp could be used to select output analog signal ( ana_out, signal written in the analog block  ) voltage between two possible values: when dig_inp=1, ana_vout=3V and when dig_inp=0, ana_out=0V

module two_voltage_mux (dig_inp, ana_vout) ;

input dig_inp ;

inout ana_vout ;

wire dig_inp ;

logic dig_inp ;

electrical ana_vout ;

real ana_vout ;

analog

if (dig_inp==0) 

ana_vout = 0.0 ;

else

ana_vout  = 3.0 ;

V(out) <+ ana_vout ;

endmodule

• How to accesses a digital event from analog block?

e.g. At every posetive edge of digital signal clock: dig_clk ( digital or descrete event), sample voltage of an input anolog signal: ana_inp, and with the sampled voltage value drive the voltage of an analog output: ana_out

module analog_sample_at_clock (ana_in, dig_clk, ana_out);

input ana_in, dig_clk; 

output ana_out;

wire dig_clk ;

real vout ;

electrical ana_in, ana_out ;

analog begin // Enter the continuous context.

@(posedge dig_clk) // Detect discrete event posedge clk1.

vout = V(ana_in);

V(ana_ou) <+ vout;

end

endmodule

e.g. Every time analog signal clock: ana_clk rise above 5V, transfer value ofinput digital signal: dig_inp, to digital output: dig_out

module analog_sample_at_analog_clock (dig_in, ana_clk, dig_out);

input dig_in, ana_clk; 

output dig_out;

logic dig_in, dig_out  ;

electrical ana_clk ;

always @(cross(V(ana_cl) - 5.0, 1)) // Code to detect the

                                    // analog event.

        dig_ou = dig_in;

endmodule

• Limitations on usage bit(s) and buses from digital block in the analog block

Discrete bit and bit groupings (buses and part selects) are accessed in the analog block as integer numbers and the limitatioon is that x and z values cannot be represented as analog integers.

In analog block, if used digital bits are set to z or x this is considered as illegal event in behavioral model, therefore it leads to simulation error. 

• How to detect an analog event from digital block?

 e.g. Detect first time analog input ana_inp, voltage rises above 5V  and store that information in digital block flag: dig_flag.  
Therefore dig_flag = 0 while voltage of ana_inp < 5V, and dig_flag becomes 1 (and stayes 1 until end of simulation) the first time voltage of ana_inp > 5V
 

bit ana_inp_crossed_5V;

electrical ana_inp;

reg dig_inp_crossed_5V_flag;

analog begin

@ (cross (V(ana_inp) - 2.5, +1 ) )

ana_inp_crossed_5V = 1;

end

always@( ana_inp_crossed_5V ) begin // Enter the digital context.

// Read value of analog ana_inp_crossed_5V within digital block

dig_inp_crossed_5V_flag = ana_inp_crossed_5V;                

end

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