NMOS: A Transistor sizing example

In one of the previous blog entries http://asicstoic.blogspot.fr/2015/04/analog-design-basics-nmos.html it is introduced a typical example of an NMOS transistor usage: a current mirror.

Here is example how to size NMOS transistors used in a current mirror copying a desired current.

Foundation of a current mirror design is the fact that:

• two identical transistors are used: meaning both have identical characteristics: VT , Kn, λ and W/L ratios

• both transistors are in saturation mode, sharing the same Vgs

 

e.g. Because the gate currents are zero for the MOSFETs, reference current IREF must flow into the drain of M1, which is forced to operate in saturation (pinch-off) by the circuit connection

( VDS1 = VGS1 )

• consequently both transistors carry an identical  Ids current

 

e.g. A  reference current IREF goes through “diode-connected” transistor M1, establishing gate-source voltage VGS. The same VGS  is applied to transistor M2, developing an identical drain current  ID2 = Iout= IREF.

Let’s assume that desired Iref = 10μA.

Here is also  Id/Vds characteristic of the NMOS transistor used and it can be safely assumed that the transistor is saturated if Vgs = Vt + 200mv.

The transistors are in saturation mode so relation of Id and Vgs is:

λ  is often assumed as 0

 

© 2011 ASIC Stoic. All rights reserved.

Analog Design Basics: NMOS

Introduction: Why do we need CMOS transistors ?

A bipolar transistor needs a base current to keep the transistor ON. And this is the main problem for bipolars in spite of the fact that its base current is small in a small signal operation.

When bipolar transistor is used in power applications, as a switch,  the base current could be really high, to keep the transistor ON, adding significantly to a power consumption ( e.g.  a need for a extended battery life in portable electronics …. ).

In CMOS technology there are two complementary types of transistors—n-channel (NMOS) and p-channel (PMOS).

NMOS: How it works ?

NMOS transistor ( n channel device ) has three terminals: gate, source and drain. NMOS conducts with a positive gate voltage, and to distinguish between source and drain terminal: a source has a lower voltage.  

As a positive gate voltage is applied, the gate attracts a negative charge forming a channel of mobile electrons connecting the drain and source regions.

• Vtn ( a threshold voltage for n channel device ) is the minimum positive voltage, when applied to a gate, that makes possible conducting electricity between the drain and source.

NMOS is OFF if Vgs < Vtn ( there is no channel formed and there is no possibility of a current flowing from drain to source  ) .

Consequently  NMOS is ON if Vgs  > Vtn ( the channel is formed and if  Vd  > Vs, there will be a current Ids .

• Veff ( effective gate-source voltage ) is: Vgs -Vtn

NMOS modes of functioning: Linear vs Saturation mode

When NMOS is ON (  Vgs  > Vtn  ) and  Vds << Veff, there is approximately  linear relationship between Vds and Ids ( the linear mode ).

NMOS in Linear mode: Ids as linear function of Vgs

But if  Vds > Veff , the channel charge concentration decreases close to the drain terminal ( the channel becomes pinched off ), making a current Ids constant (saturated ) and independent of further increase of Vds. This is the saturated mode.



NMOS in Saturation mode: Id independent of Vds because ( 1+ λ*Vds ) is approx.1 if Kn= μn * Cox *W/L then a formula of saturation Vgs = f(Id = Iref, Vds) is:

  

NMOS transistor exits linear mode and enters the saturated mode when increasing Vds reaches this point:

Vds(saturated) = Vgs - Vtn = Veff

e.g. NMOS transistor application: Current Mirror

The design of current mirror is based on "copying" current from a precisely defined reference.

In a current mirror both NMOS  transistors are in saturated mode, meaning Ids1 ( equal to Iref ) and Ids2 ( equal to Iout ) are independent of its respective Vds voltages and dependent only on its respective Vgs voltages.

• Vds1 = Vgs1= Vgs2      

Vtn +     2Id1/(Kn*( 1+*Vds1) = Vtn +     2Id2/(Kn*( 1+*Vds2)

Id1/(1+*Vds1) = Id2/(1+*Vds2)

Under assumption that: 1+*Vds1= 1+*Vds2

Id1 = Id2

 © 2011 ASIC Stoic. All rights reserved.



ASIC's Supply Pin connected to a car battery

ASIC Mix signal Specification

Automotive application: ASIC's Supply Pin connected to a car battery

ASIC Mix signal Specification

Automotive application: ASIC's Supply Pin connected to a car battery

Maximum Rating

Normal operating conditions

Error handling, Overvoltage and Undervoltage faults

Undervoltage  fault (VBAT_uv) , detection  hysteresis ( VBAT_uv_hys)  and filter time (t_VBAT_uv)

Undervoltage  fault

Undervoltage detection filter time

Implementation Note and specification requirement of hysteresis

Undervoltage detection hysteresis

Overvoltage  fault (VBAT_ov) , detection  hysteresis ( VBAT_ov_hys)  and filter time (t_VBAT_ov)

Overvoltage  fault

Implementation Note and specification requirement of hysteresis

Overvoltage detection hysteresis

October 4, 2011

Here is one detail of a possible specification of an ASIC Mix signal for automotive applications, that has an analog pin: VBAT, directly connected to a car battery.

An  implementation detail related to the specification outlined in the other blog entry: How to implement an ASIC Mix signal for an Automotive application: ASIC's Supply Pin connected to a car battery .

First assumption made here is that ASIC is working together with a microprocessor (MPU) in the system where it is used. MPU (master) and ASIC (slave) are exchanging data using one of common ( or "standard") interfaces of communication ( e.g. automotive ASIC's use a lot Serial Peripheral Interface Bus or SPI ).

In the master/slave configuration MPU can write and read registers in the ASIC using SPI bus.

Possible functionality related to the pin VBAT could include:

• supply of some ASIC's internal functions:  such as internal charge pump etc.etc.
• monitoring and reporting Overvoltage and Undervoltage faults on a car battery voltage

Here we will assume that there is already existing another ASIC's analog pin: GND, and all references of voltages in this specification are referenced to it.

Maximum Rating

Maximum rating describes that our ASIC will not get damaged ( but there is no guarantie that would be opertationel either) even if car battery voltage goes to extremes: minimum -0.3 and maximum 40V.

Pin name	Value= Min, Max
VBAT	-0.3V, 40V

Note: It is very likely that a car battery voltage connected to VBAT  with a reverse diode as protection. That is why in VBAT Maximum Rating it is assumed that negative voltage will never get more negative then -0.3V.

Normal operating conditions

Pin name	Value= Min, Typ,  Max
VBAT	6V, 14V, 40V

Note: During normal operation for the purpose of the ASIC functionality here is specified that the battery will always produce a voltage in the range of 6-40V, and a typical average value of the voltage should be 14V.

Error handling, Overvoltage and Undervoltage faults

The ASIC should monitor and report Overvoltage and Undervoltage faults on the car battery voltage ( or VBAT pin).
In the case of either Overvoltage and Undervoltage faults, a register flag vbat_ouv is set  and accessible by MPU( e.g. using SPI register read).
Once set, the register flag vbat_ouv stays 1 until there is MPU read and in the same time the value of the flag is clear by the read.
After the "clear-on-read" of the flag vbat_ouv, evaluation of Overvoltage and Undervoltage faults starts again.

Undervoltage  fault (VBAT_uv) , detection  hysteresis ( VBAT_uv_hys)  and filter time (t_VBAT_uv)

The VBAT Undervoltage fault is detected ( and the register flag vbat_ouv is set ) if VBAT voltage is LESS then  VBAT_uv, min=5.0V and max=5.5V ( typical value 5.2V ) , and this event lasts uninterrupted t_VBAT_uv time, between 250 and 350us ( typical value 300us ).

Parameter description	Parameter Symbol	Value: min, typ, max V	Comment
Undervoltage  fault	VBAT_uv	5.0, 5.2, 5.5 V	Measured on falling edge.

The time range ( between 250 and 350us, typical value 300us ) of detection/cancelation of VBAT Undervoltage fault is called Undervoltage detection filter time.

Parameter description	Parameter Symbol	Value: min, typ, max us	Comment
Undervoltage detection filter time	t_VBAT_uv	250, 300, 350 us

Implementation Note and specification requirement of hysteresis

VBAT Undervoltage fault  is going to be decided by a comparator.
Comparator should satisfy a hysteresis requirement: when VBAT is rising a voltage canceling VBAT Undervoltage fault should be higher of a voltage setting VBAT Undervoltage fault  when VBAT is falling.
Difference of the two voltages is called Undervoltage detection hysteresis.

The hysteresis is necessary to avoid that noise on VBAT cause oscillation on comparators output.   

Parameter description	Parameter Symbol	Value: min, typ, max mV	Comment
Undervoltage detection hysteresis	VBAT_uv_hys	50, 150, 250 mV

Overvoltage  fault (VBAT_ov) , detection  hysteresis ( VBAT_ov_hys)  and filter time (t_VBAT_ov)

The VBAT Overvoltage fault is detected ( and the register flag vbat_ouv is set ) if VBAT voltage is MORE then  VBAT_ov, min=30.V and max=34V ( typical value 32V ) , and this event lasts uninterrupted Undervoltage detection filter time, t_VBAT_ov= t_VBAT_uv.

Parameter description	Parameter Symbol	Value: min, typ, max V	Comment
Overvoltage  fault	VBAT_ov	32, 34, 38 V

Implementation Note and specification requirement of hysteresis

VBAT Overvoltage fault  is going to be decided by a comparator.
Comparator should satisfy a hysteresis requirement: when VBAT is rising a voltage canceling VBAT Undervoltage fault should be higher of a voltage setting VBAT Undervoltage fault  when VBAT is falling.
Difference of the two voltages is called Undervoltage detection hysteresis.

The hysteresis is necessary to avoid that noise on VBAT cause oscillation on comparators output. 

 

Parameter description	Parameter Symbol	Value: min, typ, max V	Comment
Overvoltage detection hysteresis	VBAT_ov_hys	0.5, 1, 2 V

© 2011 ASIC Stoic. All rights reserved.