SAR ADC implemented with a switched capacitor array architecture: a step by step calculation of a maximum value of the external driving source resistance to achieve a desired accuracy - an example

Many of SAR ADC’s are implemented using a switched capacitor array architecture and for an ADC like that one, here is an equivalent circuit:

Let’s approximate a driving of this type of SAR ADC input done with an equivalent circuit like this one:

Here is an example,  step by step calculation of maximum value of the external driving source resistance ( RS ) to achieve a desired accuracy of our SAR ADC.

·        First here are some basic characteristics of the SAR ADC used in this calculation/example:

·         Our SAR ADC has 8 bits output result

·         Our SAR ADC operates on 2 MHz clock frequency 

·         Our SAR ADC needs 4 clock cycles to sample a single data 

·         Our SAR ADC should have accuracy of 1/16 LSB 

·         Our SAR ADC equivalent circuit has Ri = 1KΩ, Ci=100pF

1.     Step 1 ( calculation of the sample time: Ts )

• Ts = 4 *1/2Mhz = 2μs 

• 4 represents number of clock cycles that our ADC SAR uses to sample a data
• 2MHz represents our ADC SAR operation clock frequency

       2.     Step 2  ( finding a conversion time  of our ADC with the accuracy desired)

·        It can be proven that our ADC conversion time with the accuracy desired is calculated using a following formula:

where:

o   Rt = Rs + RI

o   8 represents how many output bits has our ADC SAR

o   4 is derived from a desired accuracy.  The desired accuracy is 1/16 and 16 = 2^^4

3.         Step 3,  our ADC’s sample time should be always bigger or equal to our ADC’s conversion time with the accuracy desired :

·        

After solving this last equation per Rs, the conclusion is:

·        The analog source resistance can be no larger than 1.40 kΩ for 1/16 LSB accuracy for the SAR ADC in our example.

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